Why don't you just use the circuit design recommended by the buzzer manufacturer in their data sheet. I.E. this circuit:
This uses a simple CD4049 chip, two resistors and a small capacitor. This curcuit gives you the gain you need to make the oscillation work.
Every transistor has a current gain, usually \$\beta\$ or \$h_{fe}\$ in the datasheet. Typical values are on the order of 100. When the transistor is not saturated, then the base current and collector current are related by this factor:
$$ I_c = h_{fe} I_b $$
When the base current increases to the point where collector current can increase no more, the transistor is said to be saturated. The collector current can increase no more because it can't permit any more current -- the current is entirely limited by R1 in your diagram, and the voltage from emitter to collector is at a minimum.
When we design digital logic, we don't want to just barely saturate the transistors. We want to saturate them a lot. This provides some extra margin against variations in \$h_{fe}\$, and also takes into account that for higher frequencies (necessary for quick high/low transitions), \$h_{fe}\$ is effectively reduced.
Rule of thumb: in digital logic, design for a collector current 15 times greater than the base current.
So here, you've selected a collector resistor of 1kΩ. At saturation, the emitter-collector voltage is much less than the supply voltage, so we can estimate the collector current as:
$$ I_c = \frac{5\mathrm V}{1\mathrm k\Omega} = 5\mathrm{mA} $$
We want the base current to be 1/15th that (0.33mA), and the voltage across the base resistor will be the supply voltage, less about 0.65V from the base-emitter junction of Q1. So:
$$ R_2 = \frac{5\mathrm V - 0.65 \mathrm V}{0.33\mathrm{mA}} = 13 \mathrm k \Omega $$
Your selection of 10kΩ is close enough.
You can also scale the resistor values up, maintaining the ratio of base to collector current, but reducing the current overall. That reduces your power consumption, but also reduces the logic speed as the smaller currents are able to charge the parasitic capacitances less rapidly. This is a performance vs. power consumption trade-off that you get to make as the engineer.
Best Answer
The conditions for saturated operation and the various HFE line are various operating conditions. If you operate the transistor with 1V VCE and carrying 50mA you will see a minimum (worst case) HFE of 60. For saturated operation you need to guarantee that any transistor will work in a circuit and usually it is recommended to operate as if the worst case HFE was 10. If you look at the data sheet for saturated operation they show various conditions where they put 1/10 of the current into the base as the collector current (defined by the circuit). This is often referred to as a "forced hfe". The graph at the bottom of page 3 shows this also with forced HFE of 10.
In your circuit you have R3 as 180 ohm which will require ~30mA if Q2 is saturated. Taking the forced HFE as 10 we require 3mA into the base. This will therefore require 1.8k ohm resistor for R2. Similarly since Q1 will be expected to saturate with the current from R2 (~3ma) it needs at least 0.3mA from R1. R1 would need to be about 18k or lower.
The Forced HFE of 10 is a maximum and is not critical. You could use 5 or 15 for this circuit with no problem. A disadvantage of having a higher current into the base is that it consumes more power in the base resistor and also that the higher current will result in more stored charge in the base of the transistor which will take longer to dissipate and slow down the turn-off.
I would also put resistor from the base of Q1 to ground (maybe 10K) to assist in turn off and ensure that any leakage across the switch S1 does not cause Q1 to incorrectly turn-on.
kevin