Spice models generally do not include noise in transient simulations. The "noise" model in spice is used only in AC sweeps, where the noise power is calculated as a function of frequency. While resistor (Johnson–Nyquist) noise is in the model, semiconductor models often do not have accurate noise models. The spice diode model does include flicker noise, but not other noise sources.
For your purposes, AC analysis may be sufficient assuming that your diode has a proper model, since what you want is to see if the noise power density is flat. But, I doubt that the Zener model includes accurate noise parameters. The spice model of the diode mentioned in this question (EDZV24B) does not include any noise parameters (which are the AF, KF, and FFE parameters).
Another option (for transient simulations) is to include a voltage sources controlled by a random number. For a description of using this approach to noise modeling, this website from Giorgio Vazzana has good information. But, to follow this approach, you have to know how much noise to expect. Also, the transient simulation would not normally include noise added by the transistor.
An example noise voltage source (from the above mentioned website) is:
Vn 1 n1 dc 0V ac 1mV trrandom (1 5us 0s 125m 0m)
Design in the subthreshold regime is in my opinion not that much different from normal OTA design. If the design is going to be used in a Sallen-Key section, then the OTA will most likely be used as a buffer.
In OTA design, the \$g_m\$ of your OTA is typically given by the equation:
\$GBW = \frac{g_m}{2\pi C_L}\$
This Gain-Bandwidth (GBW) is an estimation of the frequency where the gain is 1, but it coincidentally also tells you the bandwidth of the OTA when applying unity feedback. So this will be your main equation for determining the needed \$g_m\$ for M1 and M2.
From there, you can determine the bias current for Mb by using the relationship
\$\frac{g_m}{I_{DS}} = \frac{1}{nU_T}\$
This is a slightly different formula from a "normal" strong-inversion OTA, where you'd typically use the equation
\$\frac{g_m}{I_{DS}} = \frac{2}{V_{GS}-V_T}\$
There is also a second property that could be important, which is the slew rate (SR). This is quite simple:
\$SR = \frac{dV_{out}}{dt}|_{max} \approx \frac{1}{C_L}I_{bias}\$
Choosing an appropriate slew-rate kind of depends on the situation. Make sure that you have enough bias current for both GBW and SR.
I am now going to give you one way of designing an OTA. Note that other design considerations or emphasis can be considered (eg. noise, input offset voltage, maximum speed, minimum power consumption, ...).
- Design Mb to have the desired \$I_{bias}\$.
- Don't choose a minimum length. Since Mb is designed as a current source, you want a high output impedance. Reduce short-channel effects to increase the output impedance by increasing L. Typically, you can use the relationship \$r_0 \approx \frac{V_E L}{I_{DS}}\$ where \$V_E\$ is the Early voltage. Don't exaggerate here, as W/L is fixed later, W will increase along with L!
- You choose a \$V_{GS}\$ (\$= V_{bias}\$). This means you have to tune its \$W/L\$ ratio to achieve the bias current at that specific \$V_{GS}\$. A low \$V_{GS}\$ will allow Mb to go into saturation more quickly. However, decreasing \$V_{GS}\$ means to increase its \$W/L\$ which may influence the Common-Mode transient behavior as it increases the drain capacitance as well.
- Design M1 and M2 to have the desired \$g_m\$.
- Don't use a minimum length! This has several reasons:
- It would severely inhibit the DC gain of the circuit. The DC gain is given by \$A_0 = \frac{g_m}{g_{02} + g_{04}}\$. Minimizing L means maximizing \$g_{02}\$.
- It would lead to significant mismatch between M1 and M2. For transistors that need to be matched, you best choose larger area transistors.
- Simulate the AC response of the OTA to find the GBW and tune \$W/L\$ to match the GBW. It tunes the \$g_m\$. Also note that the GBW does not change much further on, so you can tune it at this point in time.
- Typically (in non-subthreshold designs) you choose a \$V_{GS}-V_T\$ and give the transistors a \$W/L\$ ratio to achieve this while keeping track of the GBW (remember that \$I_{DS}\$ is set to \$I_{bias}/2\$ so it is fixed!). In subthreshold regime, this means choosing a \$V_{GS} - V_T < 0\$. Please note that going for lower voltages also means that \$W/L\$ will increase, meaning that the gate capacitance will increase as well. However, it will also bring you closer to the maximum attainable \$\frac{g_m}{I_{ds}}=\frac{1}{nU_T}\$ factor.
- Design the PMOS current mirror M3 and M4
- Don't choose minimum length! Minimizing L means maximizing \$g_{04}\$ which also has a negative effect on the DC gain.
- Choose an output voltage (while \$V_+=V_-\$). Due to symmetry (as both transistors drive the same current \$I_{bias}/2\$), the output voltage is the same as the voltage across the diode-connected transistor M3. Tune their \$W/L\$ ratios to achieve your desired output voltage.
Best Answer
Here are the MOSFET models from the link you posted:
The
Level=1MOSFET model structure does not model subthreshold conduction in the weak inversion state of the MOS junction. The parameter which defines the subthreshold conduction inLevel=2andLevel=3models is the "number of fast superficial states", denotedNFS. You can upgrade yourLevel=1models toLevel=2by first changing theLevelnumber (obviously) and then defining a value forNFS. You can set up a test circuit and play around with theNFSvalue until it satisfies your needs.You can also attempt to convert the
Level=1model into aVDMOSmodel, since it's a minor extension toLevel=1and also includes its own way of handling subthreshold conduction. This method is possible becauseGamma=0which means the body effect is non-existent and you can therefore permanently tie Body and Source together (which is required for VDMOS).The best way to start is to naively swap the model types out. You can do that by changing
NMOStoVDMOS(let's only focus on N-channel for now) and removing theLevelparameter, like so:If you run a simple simulation using this model, it will show some warnings in the SPICE Error Log (CTRL+L):
Let's start with the easy ones.
Gammawe already talked about and should be removed.Xjis a Level 2/3 model parameter only and shouldn't have been there in the first place...bye!Pbis simply calledVjin the VDMOS model so you just need to change the name.Toxis a little more complicated to explain off. The transconductance parameterKpis related to theToxby the following equation:$$ \text{KP} = \mu_0 \cdot \frac{\varepsilon_{ox}}{t_{ox}} $$
\$\varepsilon_{ox}\$ is a fixed number for silicon dioxide, but \$\mu_0\$ and \$t_{ox}\$ are the SPICE MOSFET parameters
UoandTox, respectfully. The trick here is that you can defineKpdirectly, or indirectly viaUoandTox. However, the trick here is that whenKpis defined it overrides the other parameters. This is a long way of saying thatToxis not used and should not be there in the first place.The three capacitance parameters are the most tricky since this is where the VDMOS structure has the greatest impact.
Cbdis the easiest as it maps directly toCjo.Cbsis non-existent in VDMOS (remember: body & source nodes shorted) so it can be removed.Cgsoneeds to be mapped toCgssomehow.Cgsois a per/meter-channel-width parameter andCgsis not. This is where I want to pause and say we've already encountered many problems/errors with this original.modeldefinition, and now we expect a per/meter-channel-width capacitance of 0.1p to be believable? I'll keep going for kicks, but if you're reading this you should skip to the next section. I'm simply going to multiplyCgsoby thedefwwhich defaults to100u. The final VDMOS capacitance parameters areCgdminandCgdmax, but sinceCgdois so small we'll simply do the same thing we did withCgsoand apply the result to bothCgdXXXparameters.Now that the model is converted, you can add the
Ksubthresparameter which defines the subthreshold conduction. I would start atKsubthres=0.1and then adjust to fit your needs. Here is what the resultant.modellooks like at the end which results in no errors/warnings:Note that for P-channel, you still write
VDMOSbut then define a parameter flag calledpchanin one of the parameters. See the built-in LTspice help page for "M. MOSFET" for more info on this.As pointed out throughout the answer, the original
.modelstatements you acquired are quite suspect. After perusing around the internet, I found a few alternative CD4007 SPICE models which you should consider.If you want to start with a better
Level=1to work through any conversion explained above, I believe this one to look slightly more believable:https://cmosedu.com/jbaker/courses/ee420L/s15/students/lej6/Project/CD4007.txt
Subthreshold conduction didn't really get modeled well until the BSIMx series of SPICE model structures were developed and expanded on. Dr. Lynn Fuller from the Rochester Institute of Technology seems to have put a lot of work into generating higher-level models for the CD4007 and other monolithic MOSFET ICs from Advanced Linear Devices. There is a paper here and presentation here which includes
Level=7models that LTspice supports. A text file with the models can be found here:https://people.rit.edu/lffeee/RIT_Models_For_LTSPICE.txt
Dr. Fuller also created a
Level=8model for the CD4007, but I can only find the NMOS version within this slide deck:http://diyhpl.us/~nmz787/mems/unorganized/SPICE_MOSFET_Model_Intro.pdf