I am trying to design a two stage amp like the one pictured above. I want the overall small-signal gain, |Av| = vo / vid = 240 V/V = (47.6 dB). I know in theory how to achieve this but am having trouble with the equations.
I know that:
Vt0 = 0.7 V
kn = 50 A/V^2
kp = 20 A/V^2
W/L = 100:1 for both NMOS and PMOS.
The output conductance at a bias point of ID = 10 mA as 200 mhos for the NMOS device and 500 mhos for the PMOS device.
If needed I can also assume that:
tox = 90 nm
Nsub = 3.7*10^15 cm^-3
Due to a current mirror the current (Id) will be the same through the differential stage (M1-M4) and the PMOS common-source amp(M7). Transistor M8 provides bias current for
M7 and functions as an active load on M7. I believe M5 and M6 act as a current source that keeps the current Io constant. RD7 and RD8 are used to venter the DC output at 0V. One or both will be zero for any calculation.
If I can get an equation for the gain through the differential amp (input: vid, output: between M2 and M4 going to M7) and an equation for the gain through M7 I can multiply them for the overall gain
What should I set R to in order to achieve an overall gain of
Best Answer
The gm of input transistor M2 is loaded by the rds of mirror transistor M4. Remembering that rds = 1/gds, we see that the input stage gain is gm_M2 / gds_M4. I will let you figure out how to include or exclude the factor of 2 that may result from the current mirror. The second stage has amplifying transistor M7 loaded by current source transistor M8. So its gain is gm_M7 / gds_M8. Now all you need to do is calculate the gm's and gds's, and perform the multiplications and divisions to get final gain from input to output. As you know, gm depends on drain current. In this circuit the drain current is "IREF" times the transistor size ratios (Wm6/Wm5) and (Wm8/Wm5). IREF is equal the voltage across bias resistor "R" divided by R. Namely, (10 volts - Vth_M5)/R. So choose an IREF that gives the gm's and gds's you need. Then calculate R = (10V - Vth_M5)/IREF.