CMOS Logic system

cmosdigital-logiclogic-level

When I was practicing logic circuit design using PMOS and NMOS , It's said that we have to use all PMOS for Pull Up Network (PUN ) and NMOS for Pull Down Network (PDN). But we know that for input voltage 0 , PMOS will allow current flow and for input voltage \$ V_{DD} \$ or logic value 1 , NMOS will allow current flow.If this is the case , why can't I solve this function $$ f=\bar{x_1}.x_2 $$ like this:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

What kind of problem this circuit can create??
Is it any problem for bias voltage ?

Best Answer

Imagine a load resistor (say 10K) from output to Vdd, and make X_1 and X_2 low. Ideally, output should be 0.0V. You can figure out what it is (not 0V).

Now imagine a 10K load resistor from output to GND and make X_1 low and X_2 high. Ideally, output should be Vdd. You can figure out what it is (not Vdd).

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Related Solutions

Electronic – An Explanation of CMOS Logic

It's actually quite simple, and it's based on two requirements:

Every node in the signal path must be connected to either Vcc or GND, to be at logical level 1 or 0 respectively;
There should never exist a conductive path between Vcc and GND, else it will short the supply and start draining a lot of current and possibly burning some parts here and there.

Therefore you must make sure that if the pull-up network is conducting, the pull-down is not. Hence their logical function must be the opposite.

What will be this CMOS logic circuit’s Truth Table

The two leftmost transistors forms a simple not gate, but it is powered only when \$V_{x1}\$ is high. Luckily enough the passgate on the right is turned on when \$V_{x1}\$ is low instead, and directly connects the \$V_{x2}\$ input to the output.

To sum it up:

if \$V_{x1}\$ is high the output is NOT \$V_{x2}\$
if \$V_{x1}\$ is low the output is \$V_{x2}\$

in a table:

x1  x2  out
0   0   0
0   1   1
1   0   1
1   1   0

that's a xor gate.

Best Answer

Related Solutions

Electronic – An Explanation of CMOS Logic

What will be this CMOS logic circuit’s Truth Table

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