Cross the output inductor trace with input power line

Yellow is the critical current flow out, not sure where it goes from the output cap, C3.

Pink is the ground return, kinda sorta, theres a few critical loops in a circuit like this, some follow the path of least resistance, some follow the path of least impedance (follow their supply trace).

Keep in mind your goal is to minimize the size of this loop and minimize the resistance between yellow/pink at high frequency, (minimize impedance to ground).

Lets just quote the datasheet since it covers all of this:

"When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most impor- tant consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. "

C1 and D2 in this case. C1 has a really, really, long path to ground for a power supply decoupling cap. Its also on the other side of the circuit from D2's ground. When your talking about high frequency PCB design when it says "tightly coupled" that doesn't mean just both tied to a ground plane. It means both ground pins are right next to each other, with a surface polygon pour connecting them and multiple via's to a ground plane right next to the pads.

Incidentally aren't your diode silkscreen's backwards?

"Next in importance is the location of the GND con- nection of the COUT capacitor, which should be near the GND connections of CIN and D1."

C3 is the output cap and its ground is roughly as far away from the other 2 as you can get.

"The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching."

Think your ok with this one, your probably better off running the trace from C3 further away from the inductor but its probably ok.

"High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the de- signer must make this trade-off. Radiated noise can be de- creased by choosing a shielded inductor."

If were you i'd just use polygon pours for most of these connections, just make sure you have appropriate filtering in place and a shielded inductor.

"The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LM2734 demo board as an example of a four-layer layout."

If using 4 layer why not reference that app note? pretty much covers using a big ol' ground pour for the critical ground return and a pour for the SW output.

That's the Cypress FX2LP USB microcontroller (I recognize it because I use it myself). If you're using the Hi-Speed USB transceiver, then you should really go with a 4-layer board. Without that ground plane right below the top layer, it will be near impossible to get the 90 ohm differential impedance that you want for the USB D+/D- lines.

http://www.cypress.com/?id=4&rID=34128 flat out states that 4 layers is required. It also states that controlled impedance is required, but in my experience you can usually get away without it, so long as you carefully research your fab's typical stack-up and work out the right width, space, and height.

http://www.cypress.com/?docID=25406 also provides more info on calculating the width, space, and height for the D+ and D- lines.

4-layers isn't that much more expensive; Advanced Circuits has a 66 each deal for 4 layer boards that I use quite often for projects that use that very chip, as opposed to the 33 each deal for 2 layers.

In regards to your actual question...use plenty of bypass caps, as close to the pins as possible. If you split the bottom layer to have VCC and GND, don't have a trace cross the split on the top layer. Keep all high-speed signals on the top layer because the via inductance can kill what fragile signal integrity a 2-layer board has.