CS4234 has two I2S data I/O lines

cirrusi2spcmpinout

I have an application where I'll be sending audio data to a codec. The CS4234 fits my needs very well, although with other I2S codecs, there have only been one data in line for the communication. The CS4234 has two input data lines and two data out lines (SDINx and SDOUTx).

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Since I only have one processor that will be communicating with the CS4234 codec, do I need to terminate or do something with the other input/output lines I won't be using? I don't think I need to do too much since the 2nd SDOUT line is also an address bit set pin (which brings up the question how would the chip know its using two SDOUT lines if the address bit isn't set…odd)

"Bonus" points if you can explain what they mean by low latency data

Best Answer

According to the datasheet, SDINx signal have an internal pull-down, so you can leave the pin unconnected.

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For the AD2/SDOUT2 you'll need to put a pull down or pull up resistor as it will set the I2C address. And as you don't use the SDOUT2, you will only have your pull up/down resistor.

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Latency is the time between the signal enter the chip and when it will go out. The "normal" path is in blue on the previous figure. You can do a lot of transformations on the signals but the latency can be high.

4.6.3 DAC1-4 Path

The DAC1-4 path includes a programmable group delay which delays the output audio signals to allow the DAC5 output to operate in feed-forward fashion, adjusting the voltage rails of the tracking power supply in anticipation of the coming audio signal

The group delay can be between 0 and 500 µs to adjust with the DAC5. And the detail for Low-latency path in green:

4.6.4 Low-Latency Path

A low-latency path is provided to allow four user selectable data signals to be routed around the group delay block and interpolation filters of the DAC1-4 path. These four signals can be present in any of the 32 slots on the two TDM streams on SDIN1 and SDIN2.

Finally from the characteristics:

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The DAC1-4 path is quite longer than the low-latency path (11/Fs against 2/Fs in single speed mode) due to the interpolation filter. The DAC5 path is adjustable to have a latency equal to the DAC1-4 path or the low latency path. Be careful to the Note 24 which state that you need to add the "Group Delay" (first block of blue path) to the specified delay.

EDIT : (forgot the address at startup)
For the AD2/SDOUT2 signal, when the internal reset signal of the chip is going inactive a small circuit will check the "value" of the AD2 input. This only occurs at the startup phase of the chip, after the startup is finish, the pin will be "tied" to SDOUT2 signal.
This is a kind of a mux working at the startup.

Many chips having an I2C bus use this trick to allow users to configure the address without adding multiple address pins. Some will even use +VCC, GND, High-Z, pull-up or pull-down "sense" to offer up to 5 configuration of address with one pin.

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