Let's say that we want to do a good job of testing this, but without going through the entire 2^32 space of possible operands. (It is not possible for such adder to have such a bug that it only affects a single combination of operands, requiring an exhaustive search of the 2^32 space, so it is inefficient to test it that way.)
If the individual adders are working correctly, and the ripple propagation between them works correctly, then it is correct.
I would giver priority to some test cases which focus on stressing the carry rippling, since the adders have been individually tested.
My first test case would be adding 1 to 1111..1111 which causes a carry out of every bit. The result should be zero, with a carry out of the highest bit.
(Every test case should be tried over both commutations: A + B and B + A, by the way.)
The next set set of test cases would be adding 1 to various "lone zero" patterns like 011...111, 1011...11, 110111..111, ..., 1111110. The presence of a zero should "eat" the carry propagation correctly at that bit position, so that all bits in the result which are lower than that position are zero, and all higher bits are 1 (and, of course, there is no final carry out of the register).
Another set of test cases would add these "lone 1" power-of-two bit patterns to various other patterns: 000...1, 0000...10, 0000...100, ..., 1000..000. For instance, if this is added to the operand 1111.1111, then all bits from that bit position to the left should clear, and all the bits below that should be unaffected.
Next, a useful test case might be to add all of the 16 powers of two (the "lone 1" vectors), as well as zero, to each of the 65536 possible values of the opposite operand (and of course, commute and repeat).
Finally, I would repeat the above two "lone 1" tests with "lone 11": all bit patterns which have 11 embedded in 0's, in all possible positions. This way we are hitting the situations that each adder is combining two 1 bits and a carry, requiring it to produce 1 and carry out 1.
Best Answer
You actually got a lot of it right. But I don't use Multisim and can't help there, much. I think I see a wiring mess around your three gates -- you should look closely there. There might be "crossed wires" in there somewhere.
Also, you do NOT need a three-input OR gate. Just a two-input one. The logic should be something like:
simulate this circuit – Schematic created using CircuitLab
I'm not showing the 7447's there. But you should get the idea for those.
As far as the displays not showing anything? That's a different problem. They come with a lamp test pin. Use it to verify that your displays are wired up correctly. The outputs are open-collector, so you must be using a common-anode 7-segment display device and NOT a common-cathode device, for example. There are lots of possible problems there. Also, if you have a voltmeter use it to probe the voltages at each of the binary lines going in to make sure they are values you expect. Etc. But mostly, forget the rest of the circuit and just focus on making sure your digit displays actually work. If they don't, nothing else will. And they are easy to test. So do that FIRST. Before screwing around with the adder stuff.