Electrical – About the critical path of ripple adder

adder

I have trouble understanding what's critical path delay of n-bit Ripple Carry Adder. In the book I read, given N-bit Ripple Carry Adder formed from N single 1-bit full adder:

  1. the critical path delay is 2N

    I know that for each single 1-bit full adder, the Cout(Carry-out)-delay is 2 and the Sum-delay
    is 3, from this observation why the critical path delay is not 2(N-1)+3 = 2N+1 (I mean the last one is calculated with Sum-delay instead of Cout-delay)? So assume that these 1-bit full adders are denoted by A(0) to A(N-1), the critical path delay is from Cin(A0) to Cout(A(N-1))? So I should not substitute the last one with Sum-delay?

  2. the delay to get the sum (Sum delay) is 2N+1

    I can understand this one, since now 2(N-1)+3 = 2N+1 should work, but isn't that this implicitly assumed that the last 1-bit full adder will be the slowest one? (You may skip this one if you want since my main focus is 1.)

Edit: I found a YouTube video explains why I mean, but I don't what whether he mean critical path delay.

Best Answer

... why the critical path delay is not 2(N-1)+3 = 2N+1 (I mean the last one is calculated with Sum-delay instead of Cout-delay)?

Because although the initial data-to-Cout delay is 3 units, the final Cin-to-sum delay is in fact only 1 unit delay, which makes the final result simply 2N.

However, the Cout from the last stage has one more gate, resulting in 2N+1.

But the terminology seems backward to me. I would call the first one the "sum delay" and the second one the "critical path".

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