I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip).
All the memory chip are on same bus so only one /CS (and /OE) shall be toggled low at same time to avoid bus conflict.
To my understanding, the MAX10 CPLD can initialize itself within 2ms at power on (based on uncompressed, un-encrypted binary, numbers I found in a datasheet).
I wanted to know what is the state of the I/O when CPLD is initializing. Are they HighZ? Low? High? Or is the state unpredictable? Some more notes:
- I use verilog "assign" to set all the critical I/O's to 1 by default (assuming registers are 0 after initialisation). Eg: "assign outputname= registername?1'b0 : 1'b1;"
- I've set all the I/O's to 3.3LVCMOS because everything is interfaced with 3.3V devices.
- The rise/fall timing requires to be less than 10ns.
Also, can someone confirm the MAX10 (10M02) CPLD has all registers cleared after initialisation? (I don't use any reset pin). I can't find any details about that on the datasheets.
Thanks for your answer / suggestions.
Best Regards,
Best Answer
As @Claudio states, the I/O pins will all be high-z during configuration.
In terms of reset, during configuration, all of the registers should be initialised to whatever default value was specified when the design was synthesized.
However I would not rely on this as your only source of reset. When you first power on the device, the state of any clock source or input source that you are using cannot be guaranteed - the clock for example may be an oscillator with some start-up time during which it may be unstable. As a result you may end up with weird metastability issues if your design has no other reset source.
If you do not have any external reset, the simplest solution would be a basic reset synchroniser chain of a few registers. The registers would be initialised to zero, and the input to the first would be a logic 1. This means that the output of the chain would hold everything in reset for a few clock cycles (as many as in the chain) after power on giving time for external I/O connections to settle down.
I would still however consider your design to see if there are any conditions - e.g. errors in control/data paths - that you consider to be fatal and use that as a secondary source to reset the system if something goes terribly wrong.