Electrical – And gate in a demultiplexer

The fact that you were given a NOR gate rather than an OR gate is a significant hint: Look for the patterns of zeros, rather than ones, in your K-map. And remember that don't-cares can be assigned the value zero or one.

Here's the K-map I came up with, based on your truth table:

    A0  0  0  1  1
    A1  0  1  1  0
A3 A2 +------------
0  0  | 0  x  0  1
0  1  | x  0  1  1
1  1  | 0  x  0  1
1  0  | x  x  1  0

If you make all of the don't cares zero, you get this:

    A0  0  0  1  1
    A1  0  1  1  0
A3 A2 +------------
0  0  | 0  0  0  1
0  1  | 0  0  1  1
1  1  | 0  0  0  1
1  0  | 0  0  1  0

Clearly, the left-hand side of the table can be taken care of by feeding not-A0 (using the inverter you were given) into one input of the NOR gate.

The remaining three zeros (Aha!) can be taken from individual outputs of the 3-to-8 decoder, whose A, B and C inputs are connected to A1, A2 and A3, respectively. Specifically, the outputs for "1", "4", and "7" should be connected to the three remaining inputs of the NOR gate.

Positive logic assigns logic '1' to high voltage and logic '0' to low voltage. Negative logic does the opposite ie. logic '1' = low voltage and logic '0' = high voltage.

A truth table only tells you the logic values, not the voltages that produce them. However if you are changing from positive to negative logic then logic '1' in positive logic translates to logic '0' in negative logic. So to convert a gate from positive to negative logic you just have to invert (negate) all the signals.

For example if you had a positive logic AND gate that you wanted to use in a negative logic circuit, you would have to put inverters on both the inputs and the output. That combination is then a negative logic AND gate, and its truth table (in negative logic) is the same as the bare AND gate was in positive logic. However its truth table in positive logic has all the '1's and '0's inverted.

De Morgan's law says that an AND gate with inverted output (ie a NAND gate) is equivalent to an OR gate with inverted inputs, and an AND gate with inverted inputs is equivalent to an OR gate with inverted output (ie. a NOR gate). This is useful when for example you only have NAND gates and need to create a NOR function, or you want to reduce the number of gates in a circuit.

Applying De Morgan's law will not change positive logic into negative logic, but it helps when you want to invert a lot of signals with the minimum number of gates. So your AND gate with 3 inverters could be converted to a NOR gate with one inverter on the output - which reduces the number of gates from 4 to 2.