Electrical – clock frequency divide by 5 vhdl

clockvhdl

i want to get the clock frequency divide by 5, can i do it with integer type or i need something else to run the decimal number?

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity divide_clk is
port( clk: in std_logic;
 clk_out: out std_logic);
end divide_clk;

 architecture behave of divide_clk is
signal count: integer range 0 to 24999999:= 0;
signal temp : std_logic := '0';
begin
process(clk)
begin
if (clk'event and clk='1') then
 if (count = 2.5) then
 temp <= not(temp);
 count <= 0;
 else
 count <= count + 1;
 end if;
end if;
end process;
clk_out <= temp;
end behave;

Best Answer

If you want to generate a 50% duty cycle divided clock in VHDL, using only rising_edge of clock, the divided clock's period should be multiples of 2. Since 5 is an odd num, you have to make use of falling_edge of the main clock too. You have to generate two 2/5 duty cycle clocks phase shifted by half period of the main clock. Then you can "OR" it to get the required clock which is of 1/5th frequency and 50% duty cycle.

Something like this:

enter image description here

Code Sample:

architecture Behavioral of divide_by_5_counter is
signal a,b : STD_LOGIC;
signal count_a, count_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin

process(clk_in,reset)
begin
if reset = '1' then
a <= '0';
elsif rising_edge(clk_in) then
if count_a = 5 then
count_a <= "0001";
a <= '1';
elsif count_a >= 2 then
a <= '0';
count_a <= count_a + 1;
else
a <= '1';
count_a <= count_a + 1;
end if;
end if;
end process;

process(clk_in,reset)
begin
if reset = '1' then
b <= '0';
count_b <= "0000";
elsif falling_edge(clk_in) then
if count_b = 5 then
count_b <= "0001";
b <= '1';
elsif count_b >= 2 then
b <= '0';
count_b <= count_b + 1;
else
b <= '1';
count_b <= count_b + 1;
end if;
end if;
end process;

clk_out <= a or b;

end Behavioral;
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