I'm trying to create a simple proof of concept regarding the configuration of our testbench (binding the correct entities to components/modules).
The structure is as follows:
top(VHDL entity)
–sub_vhdl(VHDL component)
–sub_verilog(Verilog component)
—-sub_sub_verilog_1(Verilog component)
—-sub_sub_verilog_2(Verilog component)
I want to be able to control which VHDL entity sub_vhdl binds to, and which module sub_sub_verilog_2 binds to (for simulation in Questasim).
As far as I understand with a VHDL configuration file I can control the binding of sub_vhdl and sub_verilog, but it can not define the modules lower than sub_verilog.
And if I would write a verilog wrapper for the top entity I would have the opposite problem (not being able to control the binding of components to entities of the VHDL structure).
Is there a solution for my problem ? Some scripting (for example generating the VHDL config file with a script based on the situation) is not a problem.
Best Answer
I solved it in the following way, and it should be usable for any verilog/vhdl mix no matter how complex:
1) To configure the VHDL I use VHDL configurations. One such configuration can configure from its level down in the hiearchy until a verilog module is reached. If you then load in the configuration of an entity instead of the entity itself in the RTL, you can force the use of this configuration.
2) I then pass a verilog config as a parameter when launching my simulation. For this the top level needs to be written in verilog. So if that is not the case use a simple verilog wrapper. In this verilog config you can define any path to a vhdl module and define from which library it should get it, it doesn't matter if there are VHDL layers in between.
An example:
Hiearchy:
dut_wrapper (Verilog)
-- dut (VHDL)
---- dut_sub_1 (VHDL)
---- dut_sub_2 (Verilog)
------ dut_sub_sub_1 (VHDL)
------ dut_sub_sub_2 (Verilog)
To configure all of these entities/modules:
1) Make a dut_cfg VHDL configuration that defines from which library dut_sub_1 and dut_sub_2 should come. And define this dut_cfg in the dut_wrapper instead of just the dut entity.
2) Do the same for dut_sub_sub_1
3) Make a Verilog config where you define the top level (dut_wrapper). And then overwrite any Verilog modules in the design by specifying the full path to them, and the library where they should get their version. This path can pass trough VHDL entities (use the instance names)
A tip when trying this yourself: I saw some weird behavior regarding the compile order of my design units. Sometimes it seemed the verilog config was not really used for some reason (I used Questasim 10.5c for testing). So maybe try reordering when it doesn't seem to work