Proper bypassing and grounding are unfortunately subjects that seem to be poorly taught and poorly understood. They are actually two separate issues. You are asking about the bypassing, but have also implicitly gotten into grounding.
For most signal problems, and this case is no exception, it helps to consider them both in the time domain and the frequency domain. Theoretically you can analyse in either and convert mathematically to the other, but they each give different insights to the human brain.
Decoupling provides a near reservoir of energy to smooth out the voltage from very short term changes in current draw. The lines back to the power supply have some inductance, and the power supply takes a little time to respond to a voltage drop before it produces more current. On a single board it can catch up usually within a few microseconds (us) or tens of us. However, digital chips can change their current draw a large amount in only a few nanoseconds (ns). The decoupling cap has to be close to the digital chip power and ground leads to do its job, else the inductance in those leads gets in the way of it delivering the extra current quickly before the main power feed can catch up.
That was the time domain view. In the frequency domain digital chips are AC current sources between their power and ground pins. At DC power comes from the main power supply and all is fine, so we're going to ignore DC. This current source generates a wide range of frequencies. Some of the frequencies are so high that the little inductance in the relatively long leads to the main power supply start becoming a significant impedance. That means those high frequencies will cause local voltage fluctuations unless they are dealt with. The bypass cap is the low impedance shunt for those high frequencies. Again, the leads to the bypass cap must be short else their inductance will be too high and get in the way of the capacitor shorting out the high frequency current generated by the chip.
In this view, all your layouts look fine. The cap is close to the power and ground chips in each case. However I don't like any of them for a different reason, and that reason is grounding.
Good grounding is harder to explain than bypassing. It would take a whole book to really get into this issue, so I'm only going to mention pieces. The first job of grounding is to supply a universal voltage reference, which we usually consider 0V since everything else is considered relative to the ground net. However, think what happens as you run current thru the ground net. It's resistance isn't zero, so that causes a small voltage difference between different points of the ground. The DC resistance of a copper plane on a PCB is usually low enough so that this is not too much of a issue for most circuits. A purely digital circuit has 100s of mV noise margins at least, so a few 10s or 100s of μV ground offset isn't a big deal. In some analog circuits it is, but that's not the issue I'm trying to get at here.
Think what happens as the frequency of the current running across the ground plane gets higher and higher. At some point the whole ground plane is only 1/2 wavelength across. Now you don't have a ground plane anymore but a patch antenna. Now remember that a microcontroller is a broad band current source with high frequency components. If you run its immediate ground current across the ground plane for even a little bit, you have a center-fed patch antenna.
The solution I usually use, and for which I have quantitative proof it works well, is to keep the local high frequency currents off the ground plane. You want to make a local net of the microcontroller power and ground connections, bypass them locally, then have only one connection to each net to the main system power and ground nets. The high frequency currents generated by the microcontroller go out the power pins, thru the bypass caps, and back into the ground pins. There can be lots of nasty high frequency current running around that loop, but if that loop has only a single connection to the board power and ground nets, then those currents will largely stay off them.
So to bring this back to your layout, what I don't like is that each bypass cap seems to have a separate via to power and ground. If these are the main power and ground planes of the board, then that's bad. If you have enough layers and the vias are really going to local power and ground planes, then that's OK as long as those local planes are connected to the main planes at only one point.
It doesn't take local planes to do this. I routinely use the local power and ground nets technique even on 2 layer boards. I manually connect all the ground pins and all the power pins, then the bypass caps, then the crystal circuit before routing anything else. These local nets can be a star or whatever right under the microcontroller and still allow other signals to be routed around them as required. However, once again, these local nets must have exactly one connection to the main board power and ground nets. If you have a board level ground plane, then there will be one via some place to connect the local ground net to the ground plane.
I usually go a little further if I can. I put 100 nF or 1 μF ceramic bypass caps as close to the power and ground pins as possible, then route the two local nets (power and ground) to a feed point and put a larger (10μF usually) cap across them and make the single connections to the board ground and power nets right at the other side of the cap. This secondary cap provides another shunt to the high frequency currents that escaped being shunted by the individual bypass caps. From the point of view of the rest of the board, the power/ground feed to the microcontroller is nicely behaved without lots of nasty high frequencies.
So now to finally address your question of whether the layout you have matters compared to what you think best practices are. I think you have bypassed the power/ground pins of the chip well enough. That means it should operate fine. However, if each has a separate via to the main ground plane then you might have EMI problems later. Your circuit will run fine, but you might not be able to legally sell it. Keep in mind that RF transmission and reception are reciprocal. A circuit that can emit RF from its signals is likewise susceptible to having those signals pick up external RF and have that be noise on top of the signal, so it's not just all someone else's problem. Your device may work fine until a nearby compressor is started up, for example. This is not just a theoretical scenario. I've seen cases exactly like that, and I expect many others here have too.
Here's a anecdote that shows how this stuff can make a real difference. A company was making little gizmos that cost them $120 to produce. I was hired to update the design and get production cost below $100 if possible. The previous engineer didn't really understand RF emissions and grounding. He had a microprocessor that was emitting lots of RF crap. His solution to pass FCC testing was to enclose the whole mess in a can. He made a 6 layer board with the bottom layer ground, then had a custom piece of sheet metal soldered over the nasty section at production time. He thought that just by enclosing everything in metal that it wouldn't radiate. That's wrong, but somewhat of a aside I'm not going to get into now. The can did reduce emissions so that they just squeaked by FCC testing with 1/2 dB to spare (that's not a lot).
My design used only 4 layers, a single board-wide ground plane, no power planes, but local ground planes for a few of the choice ICs with single point connections for these local ground planes and the local power nets as I described. To make a long story shorter, this beat the FCC limit by 15 dB (that's a lot). A side advantage was that this device was also in part a radio receiver, and the much quieter circuitry fed less noise into the radio and effectively doubled its range (that's a lot too). The final production cost was $87. The other engineer never worked for that company again.
So, proper bypassing, grounding, visualizing and dealing with the high frequency loop currents really matters. In this case it contributed to make the product better and cheaper at the same time, and the engineer that didn't get it lost his job. No, this really is a true story.
There isn't one.
That said, there are some thing I've gathered over time. What you do with the ground planes depends heavily on what you're trying to do. You could be trying to provide low impedance paths, or you could be trying to isolate one area from another, or you could be trying to deal with EMI.
There certainly is a performance penalty for doing it wrong, but you may not really care unless you're dealing either with high frequency circuits or precision analog work. The number of fluctuating bits of the ADC reading with inputs grounded, or the spectral purity of an RF signal as measured by a spectrum analyzer will tell you how wrong you are with any design. It's generally impossible to get it 100% right (datasheet spec) unless you've a system as simple as their test circuits.
The most complicated ground connection problems have to do with RF frequencies, and with signals that are either weak or are passing through traces which are susceptible to EMI coupling in that frequency. At microwave frequencies, a centimeter is enough to make a very effective antenna and mess with things. I remember a professor of mine once told me that when he was working in the industry, they'd leave plenty of points where two grounds could be shorted together, and then an engineer would test each of them one by one to see which gave the best performance. They were working with high frequency (microwave) circuits.
Typically, there's three kinds of 'ground plane' like elements you'd be wanting to short.
Real ground planes. For some reason or the other you've got many of them, and you want to connect them together. This is probably the most common occurrence of the problem in the run of the mill circuits.
Ground / guard traces that are running along with signal lines which may be providing a return path, guarding a high frequency signal or one bound to/from a high impedance source or sink. This could either be to prevent signal leakage or to prevent EMI coupling.
Multiple ground planes which are actually the same ground.
To begin with, you should understand that there isn't really a universal ground, and also that different grounds in the same circuit arent necessarily the same ground. A typical example you'd come across is a datasheet for an ADC that talks about analog and digital grounds. This is to make sure that the oh so noisy digital circuitry doesn't mess with the high resolution ADC you've paid extra for. Different kinds of circuits have different characteristics when it comes to their interaction with the ground. Since digital circuits are characterized by a sudden spike in current at each clock, they tend to be particularly noisy at the clock frequency, and subsequently at harmonics and sub harmonics. Bypassing capacitors are supposed to deal with this, but they rarely do a thorough enough job to get milli or microvolt resolution possible from the ADC using a relatively quieter analog ground with much less switching going on.
Similarly, power grounds tend to be noisy because loads like motors and solenoids tend to be noisy, either because of effects of commutation or things like PWM. The high currents involved and the finite ground resistance (even a chunk of copper has some resistance) means that the transients showing up on the power ground tend to be higher. Sometimes high enough to completely screw up your encoder measurements while controlling a motor for instance.
The goal, then, is to isolate these grounds best you can. That means that they dont overlap, at all. You don't put analog ground on the top and digital ground at the bottom. Everything to do with analog goes with the analog ground, and everything to do with the digital goes with the digital ground in separate areas of the pcb. When the goal is isolation, you connect the planes together at a single point. More than one point can be disasterous since it leads to current loops and hence EMI problems and unintended antennae. The point where the grounds are all shorted is usually referred to as the star ground point of the circuit and is as close as you're going to get to a circuit wide ground. Generally, these should be shorted as close and centrally as possible to a place where the two circuits interact, usually an ADC or DAC. In truely haphazard designs, you'd short them near the supply and pray for the best. This is type 1.
In type 2, you have some sort of a guard trace. If the trace is at ground, then you're probably worried about EMI and not leakage. In the case of leakage, you'd want to drive the guard at close to the signal level. In both these cases, you want the guard to be as low impedance to the source as possible. This means multiple vias dropping down to the ground plane at regular intervals, if the trace is to be grounded.
The third and somewhat less exotic variety, and really is sort of just stating the obvious. This has to do with the vias taking decoupling caps to ground or the random vias shorting top and bottom ground planes. Once you've created a star ground and isolated the different areas, you want each ground to be as uniform as possible. For example, you don't want there to be a measurable potential difference between two corners of analog ground plane. You do this by providing a low impedance path to the star ground - each pin or pad that needs to be grounded goes to the plane which provides it a straight shot to the star ground point. Having the plane has the added advantage of providing a return path under each signal trace, which avoids current loops forming which may act as antennae. In cases where the ground plane must be broken, but you need to have a return path, you would provide an alternate route through another layer. If you have multiple planes with ground in the same area (note:these must be the same ground), periodic vias can help reduce impedance slightly.
I hate rules of thumb, I abolish them wherever I work. It's far better to understand why. With that said your goal in a good decoupling strategy should be to minimize the impedance across your frequencies of interest. This translates into wanting to minimize inductance which usually means reducing the loop area or reducing the impedance of the connecting traces/planes/vias. So you can create a nice low inductance path between your chip pins and that cap by placing them on the same layer and running wide traces to it.
Then you want a nice low inductance path to your power planes. One set of vias right at the cap seem like a nice idea. Two sets of vias would of course lower your inductance further since the inductance of each via would be in parallel with each other. (I often do Via in pad but I have the luxury of using those processes. You may too if you're already at an eight layer board).
So with that said and you being a designer who understands your system you can now make your own tradeoffs. In your structure above it looks to me like your loop area is unnecessarily long so I would look for ways to reduce it. But maybe you have other reasons for that so just keep in mind that you want to reduce the loop area and impedance between the caps, pins and the power planes.
If you want to know if what you've done is "good enough" or even more difficult optimal before you build it you will have to understand your dynamic current requirements and then do some level of simulation. Otherwise your options are really to try it, or over design it a bit to give yourself some margin.