Electrical – Designing Common Source Amplifier with NMOS transistors

If the real question is "fill in the component values to get maximum output voltage without clipping for the given input signal.", then this question can't be answered except in the specific case of making C4 zero (removing it). Can you see why? Also, you don't have any choice over the DC gain. You can make the AC gain higher than 1, but if you're stuck with this circuit topology you really can't make it all that predictable. Can you see why that is?

If I was given this problem, I'd probably write a answer explaining why this topology is unreasonable for achieving the goal, which is also too vague to be a real spec. I'd back that up with a detailed analisys and critique of the circuit, explaining exactly what the problems are, what important specifications are missing, and why a predictable result is not possible. Maybe I'd flunk the question, or maybe I'd get extra credit. However, I'm not going to engage in irresponsible engineering just to tell the instructor what most will assume he wants to hear.

I think what the instructor wants you to realize is first what gain you actually need, then how to adjust the component values to achieve that gain.

First let's look at the gain required. The input is only specified to be "10 mV". That leaves a lot unsaid. I'd probably take that as being a AC 10 mV RMS signal. When looking at amplifier clipping, it's the peaks that matter. The first thing you should think about is what peak to peak voltage is implied by "10 mV" in this case. I'd consider that to be at least a sine wave, but if it's something like a audio signal you will need some headroom past what a sine wave would peak at for the given RMS voltage. Think about this carefully. What peak to peak input voltage are you going to assume?

Next, look at what the output can do. Q2 is biased by ground, so the extent of the collector voltage will be roughly from ground to the 10 V supply. For good design, I'd probably leave a little room so that the worst case peak-peak input resulted in about 9Vpp out.

From the above two analisys, you should be able to decide the voltage gain this amplifier needs. As others have noted already, the first stage is a emitter follower, which will have a voltage gain of basically 1. It can be used to lower the impedance of the input signal, but it's not going to provide any voltage amplification. Do all the parts really need to be there? Put another way, consider that you could specify part values as 0 (short) or infinite (open). Consider what exactly RC1 is doing for you, for example.

All the voltage gain is going to come from the second stage (the circuit around Q2). C2 helps in that it decouples the DC operating points of the first and second stages. Can you see how you don't really have much choice over the DC voltage gain of this stage, and how you don't have any choice at all over the DC gain of the whole amplifier? In fact, you're not going to get more than a DC gain of about 1 from this stage. This may not be so obvious. Take a look at it carefully and tell us why.

C4 can effect the AC voltage gain, but can you make that predictable and not a function of the frequency?

Overall, this is a much more tricky problem than others seem to taking it as. I suspect that the instructor messed up or there are additional specifications you haven't given us. Or possibly the instructor wants you to find the problems in what looks like a straight forward assignment at first glance.

For the mosfet to work as an amplifier, it needs to be biased in the saturation region, ie Vgs needs to be > Vt (4.15V). And it needs to remain so irrespective of excursions of +/- 100mV of v in.