I need to create a JK Flip-Flop using a D Flip-Flop, a 2-to-1 line MUX and an inverter. I wasn't really familiar with latches and Flip-Flops, but I understand the difference and how Flip-Flops are edge triggered with a clock pulse whereas latches are instantaneous with input changes. Now when I was doing some digging into D-type Flip-Flops, I came across two different representations that I'm having a hard time differentiating. The first is very straightforward and seems to be the standard representation.
This computes fine for me. I can trace and follow it and fully understand how it works. Most common name I could find for it was simply D-Type Flip Flop.
However when I look further, I cannot differentiate between the name of the previous D-type Flip-Flop and this one:
Everywhere I look this one is defined as Edge-Triggered D-Type Flip-Flop, but I thought where a synchronous circuit uses a clock changes were always edge-triggered? Can someone please explain the difference and how to go about tracing the second one?
Best Answer
The first one is not master-slave; you would have to cascade two copies of that circuit (with the clock inverted between them) to get the same functionality as the second circuit, which is indeed a master-slave (edge-triggered) flip-flop.