I have a doubt regarding the usage of the ADD instruction in Intel 8086 microprocessor.Don't ADD AX,BX and ADD AX,[BX] mean the same thing?
Electrical – Doubt regarding ADD instruction of the 8086 microprocessor
microprocessor
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Instructions are made up of a variable number of "words" and those words are made up of bits. In the case of the 8085 architecture, you can have instructions that are one, two, or three words long, and each word is 8-bits. Those bits are divided up into fields based on your instruction set. What fields there are and what those fields mean is usually contextually sensitive based on the value of one field that always has the same meaning. Typically this field is referred to as the "op code." You should read in detail at least chapter 8 of the linked pdf to get a thorough understanding.
In the case of instructions that operate on registers and store their results in a register, the source and target registers need to be identified in some fields in the instruction. In the case of an instruction that adds a constant to a register and stores the result in a register, the registers still need to be identified, but the constant also needs to be encoded in the instruction in its own field. In instruction set architectures, the term "immediate" is often used to mean a "constant value." In case of instructions that read from or write to memory, the location in memory may have to be encoded within the instruction.
That's the basic idea, hope this helps. For future reference, a good search term for questions like this is "Instruction Set Architecture" for your processor.
Edit Re: STA 4200
The STA instruction is described on page 3-61 (pg 117) of this Assembly Language Programming guide for 8080/8085 processors.The three bytes are:
- Byte 1 = OpCode (00110010)
- Byte 2 = Low Address Byte
- Byte 3 = High Address Byte
STA is the "Store Accumulator Direct" instruction, and what it does is copies the value of the Accumulator into memory at the 16-bit address composed from Bytes 2 and 3.
Generally speaking, a cache is a layer which abstracts the access to memory. When a piece of information is needed, it is specified by its address. All entries in the cache are tagged with the memory address of the datum that they hold. When the processor requests a datum, the cache control circuitry searches the cache for a matching address.
If the cache is fully associative than the entire address (except for the least significant bits) is matched against the entire cache. This matching is not a linear search, but an associative lookup. The cache entries somehow compare themselves to the address in parallel and one of them announces itself as a match.
If the cache is set associative then some of the address bits are used to directly select a bucket. For instance if there are 16 buckets, then four bits from the address can be taken as a bucket address 0 to 15. Then an associative lookup for the address takes place within just that bucket. This means that for any given memory address, we know which cache bucket it maps to, but not which specific cache line within that bucket.
If a cache is direct mapped then some of the address bits are used to select a single cache line, which either holds data for that address or not. So there is no associative lookup. Each address is mapped to a just a single cache line. (If a program alternately accesses two items at different addresses that map to the same cache line, the performance is bad. This is the worst/cheapest kind of cache.)
When there is a cache hit, then the item can be quickly supplied to the requesting circuit out of the cache. If there is a miss, then a memory access cycle has to be executed. The data is not only given to the requesting circuit, but also installed into the cache (replacing something else that has not recently been accessed).
Instruction caches tend to be specialized, to take advantage of the access patterns and the structure of the data. The cache may work at a higher level, combined with the instruction decoding. The requesting circuit asks not simply for an instruction opcode, but it demands a decoded instruction. The combined caching and decoding circuitry provides it. The idea is the same. Take the address and find a decoded instruction for that address. If it's not found in the cache, then it must be fetched and decoded.
So the answer to the question "how does the processor know" is that the processor is divided into logical units, and these units provide services to each other. The units which request data from memory do not have to be aware of the cache. The responsibility is put into the cache control circuitry. I.e. inside the ovearall processor there effectively a smaller processor which in fact "does not not know" that the data is in a cache.
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Best Answer
ADD AX, BX
This adds the contents of register BX to the contents of AX and leaves the result in AX.
ADD AX, [BX]
This one uses the contents of register BX as an offset address to a memory location. The 16-bit contents of that memory location is added to the contents of AX and leaves the result in AX.