Electrical – FPGA flash memory programming

As Socrates says, this is a JTAG problem. Check signal integrity on the JTAG lines. Check the voltage level and especially the clock. If there is ringing during the rise of the clock, it will try to clock in 2 bits instead of one. This will cause JTAG to fail.

Regarding the warnings:

Warning (20028): Parallel compilation is not licensed and has been disabled

means it Quratus II using one core. It will not take long for such a simple design

Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground' This means don't connect other chips to other pins.

Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.

This isn't necessary for a small design. It is useful for large designs and partial recompilation.

Warning (306006): Found 1 output pins without output pin load capacitance assignment Info (306007): Pin "pin_name2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis

This means the reported timing will be faster than it really is.

Warning (332068): No clocks defined in design.

That makes sense; you don't have any clocked registers.

I think from your question you already understand this, but for clarification, this is my usual terminology:

• Programming implies altering some non-volatile device
• Configuration is what the FPGA does when it starts up - it loads its volatile internal memory from non-volatile external memory.

So, as you surmise, the system needs a non-volatile device of some sort which you program on the production line. To Clarify your comment on the USB blaster, it is not a chip... it's a "pod", so you'd have one for your programming station, not one per board:

Anyway, back to the non-volatile storage options:

• The "Almost-zero-engineering required" approach uses Altera's configuration flash devices, which are JTAG programmable using something like a USB blaster. You just wire them up like the datasheet says, and away you go. They cost more per MBit than other options, though, so are not often used in volume production.

• One more usual approach is a "normal" SPI flash chip. The Cyclone user guide configuration section will list some which are compatible with it, and I believe you can also use the Quartus software to program them via the JTAG of the FPGA they are connected to. More engineering involved, checking you have the right device etc. Also, if you are in volume production, you may not want to be using Quartus on the production line, which which case you may have to provide a separate programming header for the flash chip, and some hardware+software to drive that.

• If you have a microcontroller in your system (even on another board...) you could connect that up to the FPGA's JTAG or configuration pins and store the FPGA bitstream in the micro's flash. More engineering involved as you have to have some software to "boot" the FPGA. however, it can make in-field upgrades easier, as often the micro is set up to receive software upgrades already, whereas updating the flash when it hangs directly off the FPGA is often an "opening the box" experience!