# Electrical – Gain and Rise Time with Transimpedance Amplifier Circuit

amplifiergainrise timetransimpedance

I'm working with a transimpedance amplifier circuit using a Silicon Photomultiplier.

This circuit is the recommended transimpedance circuit for reading SensL's silicon photomultiplier. A link to their product page is below. We used this circuit as a starting point for our actual circuit below.

These amplifiers are on separate channels, and the only thing that they have in common is the -30 V bias and the op-amp power supplies. Otherwise, they are independent of each other. Below is an image of the layout.

The board is a 6-layered board with its unique shape to separate the SiPMs from the power header at the other corner while keeping the SiPMs close to each other. The outputs are are separated on individual layers, so they do not reside on the same plane except at the end when they have to go to the bottom layer to reach the connector. Despite the appearance, all six layers are ground planes, just shown unfilled for routing illustration.

Through working with circuits like this, I'm kind of getting an understanding of how the circuit works, converts a current signal into a voltage signal, but I'm having trouble trying to understand the relationship between the feedback elements, in both the frequency domain and the time domain to relate the gain, the rise-time, and the filtering.

From what I calculated, the gain of the output signal is primarily controlled by Rf, so nothing new there. In regards to the filtering, Rf and Cf form a low pass filter: Rf / (1+ [j*2*pifRf*Cf]), and this simplifies to 1/(1+[j*2*pifRf*Cf]) since Rf is just the gain of the signal. In regards to the rise time, is it correct to view it as a basic RC circuit considering only the feedback resistor and capacitor components, or would doing so miss something?

The reason I'm asking is because I'm trying to provide a high gain for the output of the amplifier while keeping the rise time as small as possible. With the nominal values shown in the schematic, we're getting around 20-30 ns. My team and I have tried using smaller capacitors, 1 pF, 0.5 pF, 0.3 pF, and 0.1 pF in place of 3 pF, but the results are the same (aside from the increased noise) with the rise times at 28 ns. If we reduce the capacitance, surely the rise time would get smaller, but for it to stay the same seems odd. Again, the goal is to keep the rise time low while keeping the gain high.

http://sensl.com/products/j-series/

To be more specific, we are using a 6mm high-density silicon photomultiplier, the MFJ60035-TSV. Rise time for the anode-cathode output is 300 ps, and the capacitance at the anode output is 4000 pF. It doesn't say anything about capacitance at the cathode. Max current is 15 mA, while the active area is 6.07 mm x 6.07 mm. The device requires a typical breakdown voltage of 24.5 V, so that's why we have that large -30 V bias at the anode.

EDIT: Here is the datasheet for the amplifier, along with the product page for the resistor:

https://www.digikey.com/product-detail/en/yageo/RC0402JR-07470RL/311-470JRCT-ND/729429

The resistor is nothing special, being 0402 and rated for 1/16 watts. In regards to the op amp, I don't know much about op amps aside from the ideal one, so parameters such as the slew rate are new to me. The slew rate is 290 V/microsecond, but what does that have to do with the rise time?

Below are the capacitor parts that were used:

https://www.digikey.com/product-detail/en/murata-electronics-north-america/GRM1555C1H3R0WA01D/490-8204-1-ND/4380498

https://www.digikey.com/product-detail/en/kemet/CBR04C108B5GAC/399-6153-1-ND/2732136

https://www.digikey.com/product-detail/en/murata-electronics-north-america/GRM1555C1HR50CA01D/490-5959-1-ND/3721316

https://www.digikey.com/product-detail/en/samsung-electro-mechanics-america-inc/CL05C0R3CB5NNNC/1276-1618-1-ND/3889704

https://www.digikey.com/product-detail/en/murata-electronics-north-america/GJM1555C1H1R0BB01D/490-6073-1-ND/3845273

They were chosen for their size and voltage rating. I thought that 50 volts would be plenty for this application.

EDIT: Below is a scope waveforms of the circuit. This image should be the base value of 3 pF. I apologize for the quality, but it was all I was sent. I will try and see if I can get a better one later on.

Below is another waveform, again 3 pF. These waveforms are from two separate boards. The signal in green is from a board containing one SiPM, while the purple signal comes from a board holding 4 SiPMs. Only one SiPM is active on both of the boards. I think that the amplitude difference might be due to the -30 V bias being spread out across multiple SiPMs.

Here is an image of some other waveforms with different capacitors. This one below contains waveforms of signals with Rf being 470 ohms and Cf being 0.3 pF and 0.1 pF. The green signal is 0.3 pF while purple is 0.1 pF. Both rise times are about the same at around 30 ns.

Again, with the following picture, Rf is still 470 ohms. Green is 1.0 pF, while purple is 0.5 pF. Rise times here are approximately 27 ns.

Given the 'variance' on these rise times for the different valued capacitors, it seems that there is some upper limit for the TIA. Decreasing the capacitance past 3 pF seems to do nothing for the rise time and just increases the noise, though I don't really understand why this is.

EDIT: Since someone brought it up, ideally, I was expecting a rise time of 10 ns given the values. Below is a simulation of my circuit. The SiPM model is a model provided by the manufacturer, and the voltage bias is already taken care of in the model so there's no need for a -30V bias at the anode. I had to give it an external pulse in order to 'activate' the SiPM, so it was just a simple 5 V pulse. You can see it in the figure in green. The blue is the output signal, and it's rise time is 9.98 ns given a 50 ohm output load.

I mentioned this in comments, but I wanted to put it in the body so it's more concrete. My team and I did some test involving changing out the feedback resistor while keeping the capacitance the same at 3 pF. By reducing the feedback resistor, we were able to make the rise time faster at the expense of a smaller voltage gain. Making Rf 235 ohms reduced the time from 27 ns to 18 ns, and reducing it down to 50 ohms got us a 10 ns rise time. Now, we're trying to do the opposite, reduce the capacitor while keeping the resistor the same at 470 ohms, but it seems odd that anything below 3 pF still results in the same rise time of ~30 ns.

If we reduce the capacitance, surely the rise time would get smaller, but for it to stay the same seems odd. Again, the goal is to keep the rise time low while keeping the gain high.

There are several possible causes:

• It comes from the sensor.

You got the docs. They seem to require an account on the manufacturer's website.

• Layout

Capacitance at feedback node, supply decoupling, etc. You can post a layout image.

I'm going to assume that the opamp isn't driving a heavy capacitive load like a long cable, that everything is terminated properly, etc. You can try a fast X10 probe on the output without any cable, if in doubt.

• Opamp slew rate

OPA656 is specced for a slew rate of 290V/µs. Note its rise time of 1.5 ns (datasheet page 5) is specced for a 0.2V step only.

You don't say how much voltage rise there is in your rise time, so I can't tell. Going from 0V to 10V in 10ns requires 1000V/µs, but going from 0 to 1V in the same time only requires 100V/µs.

So, you can try to change the 470 ohms resistor to a lower value, say 47 ohms. Try to use the lowest cap that will work for Cf. If the rise time gets faster, then the culprit was the opamp slew rate limit. If nothing changes, then it is the sensor.

If your problem is opamp slew rate, then you'll need a faster opamp.

EDIT

The resistor is nothing special, being 0402 and rated for 1/16 watts.

The resistor is wrong. You selected thick film, this has higher noise, plus the noise is current-dependent. besides, it is 5%, and 100ppm/°C. Thick films are meant to be cheap.

Use a thin-film resistor. Like 1%, with good tempco (I don't know what precision you need). Anyway, thin film will have lower noise. You can also use MELF metal film, but I'm not sure about the MELF parasitic L/C, unless a RF guy chimes in. So, better stick with thin film.

Also, I hope all caps in the signal path (including 30V bias filter) are C0G, as High-K ceramics like X7R have voltage-dependent capacitance (ie, distortion), low precision, and also act as excellent piezo microphones.

In regards to the op amp, I don't know much about op amps aside from the ideal one, so parameters such as the slew rate are new to me.

OK, that explains it.

The slew rate is 290 V/microsecond, but what does that have to do with the rise time?

Well, when the output of the opamp must move from, say, 0V to 3V, it cannot do so instantly. The slew rate is the maximum rate of change of the output voltage.

So, in this example, with 290V/µs, we get 3V step divided by 290V/µs = 10ns. It cannot go faster than this.

In fact, it will be slower. Slewing is a non-linear operation, during which half of the input stage of the opamp is off and the other half is fully on, because the error voltage between opamp inputs exceeds the maximum for linear operation.

Once the output gets close enough to the target value, the input stage begins to work normally again and regains control of the ouput. But this takes a while (not so much on a fast opamp, but still not zero time).

Then the output has to settle (see settling time in datasheet).

Slew rate is why your rise time depends on the amplitude of your step, in volts. When the opamp goes into slew rate limit, rising to the top of a higher step takes longer. You still haven't said what the step voltage change was, btw...

So you either need a faster opamp, or a smaller voltage step (lower gain). Sometimes one opamp won't do the job, and you can use two in series, each providing part of the gain. Only the first opamp matters for noise, as the second one works on an amplified signal.

Layout

The layout is a problem. I'll explain.

Just because you put each trace on a separate layer does not mean they are isolated. You put a GND fill on each layer, but you did not connect these layers together with lots of vias. In presence of high speed signals, inductance matters.

At rise times of 1ns we're in GHz land. One via is 1nH, which is 6 ohms. But your vias are very few and far in between, so your ground planes are connected together with unspecified, and rather high inductance. Planes also are capacitors, so they couple. L and C together also will make a tank circuit, which will ring. You will also get tons of crosstalk.

(please relax, I'm not bashing you, OK, this is exotic stuff)

Next, power integrity.

So you got an input power connector... There should be a filter there, common mode and/or ferrites in the power lines to make sure the high speed signals do not use the power wires as antennas.

Your opamps' supply decoupling caps are at the power connector, and power is routed through traces. These traces have at least 10-20 nH inductance, which at 1GHz is... tons of inductive ohms ! When the opamp attempts to draw current to drive your fast pulse, its supply voltage will collapse (and it will also kill its neighbour's supply, since there is one cap for everyone). Fast opamps need their own personal decoupling caps, as close as possible.

Same for the -30V decoupling, use one per sensor, and put them close! Considering the length of the trace to the -30V decoupling cap, the current pulse from the sensor will reach it... well, about 150-200ps/inch... well, the 500ps rise time will be finished before the wave propagates to the cap, it will then reflect back to the sensor and produce a false echo.

Looks like you're in for a board respin !...