How do I calculate the gate count and dynamic power for a design in Xilinx? I am doing a project on Xilinx using ISE 14.7. I do not understand the gate count and dynamic power for the design.
Electrical – Gate count and dynamic power calculation in Xilinx
xilinx
Related Solutions
Add (and use) a reset signal.
Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5). AFAIK, the @initial block is ignored.
However, things are chaotic when the FPGA starts up, because:
- The GSR is asynchronous.
- PLLs are not locked
- Not all PLLs lock at the same time
- There are race conditions everywhere
So the initial Flip-Flop values after the GSR are not enough.
Create a module that generates a reset signal for each clock domain. You can create it by by AND'ing relevant asynchronous reset signals, such as an external reset pin, PLL/DCM locked signals, and using it with a synchronizer, as follows:
(Source: How do I reset my FPGA?)
If you're looking for power consumption, the easiest way to measure it is to load your design onto an FPGA, connect it to a power supply through a multimeter, and take note of the power. If you're trying to measure very small currents, you may need to use more precise equipment.
Best Answer
You can't get an ASIC-equivalent gate count directly on an FPGA. What you can get are lists of what FPGA primitives are used by the design. Check the _utilization_synth.rpt and _utilization_placed.rpt reports.
As for power consumtion estimates, check the _power_routed.rpt report. This will list the static and dynamic power, as well as temperature range estimates if you have properly specified the heat sink.
Edit: oops, you're using ISE. Primitive count will be in the .map, .mrp, and .par files. For power, you will need to run the power analyzer. See http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_xpower_analyzer.htm .