Electrical – How to check receiving 16-bit data using a serial terminal

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal software on windows pc. I did a research on google and found many terminals that only allow for 8 bits of data with parity check + start + stop bits, in my case its 16 bits. so how can I monitor this 16 bits of data using a terminal?

Updated,

I have performed something like this (pseudo-code) and did not work

X_16_bit –> 16 bit data
X_16_bit –> AB

A —> upper 8 bits

B —> lower 8 bits

this 16-bit X_16_bit updates at every 0.5 seconds. in a 50MHz clocked process, in the same process, I do below operation. (did not work)

x <= 0; and y <= 0; are initialized as varibles inside below process

process(clk_50)
variable x  : STD_LOGIC:= '0';
variable y  : STD_LOGIC;
variable A  : std_logic_vector(7 downto 0)              := x"00";
variable B  : std_logic_vector(7 downto 0)              := x"00";
variable X_16_bit   : std_logic_vector(15 downto 0)             := x"0000";

begin

                  ------------------------
***THE CODE THAT calculates X_16_bit at every 0.5 seconds*** 
                   -----------------------

//SPLITTING code runs in 50MhZ clocked process 

if (x ='0'){ // stop A and B is being mixing with a new value
 A :=  X_16_bit(15 downto 8);
 B :=  X_16_bit(7 downto 0);
}

if (x='0'){ // 1stly send upper 8 bits
  tx_data <= A;
  y:=1;
  x:=1;
}
if (y='0'){ // 2ndly send lower 8 bits 
  tx_data <= B;
  x:=0;
}
y:='0';
end process;

the below error was solved,
tx_data is a signal that used to transmit data in tx transmitter process
i got error

 Error (10028): Can't resolve multiple constant drivers for tx_data

UART transmitter is another process I use baud rate 19200 even parity
the VHDL I have used is in this link

UPDATED

process(clk_50)
variable x  : STD_LOGIC:= '0';
variable y  : STD_LOGIC;
variable A  : std_logic_vector(7 downto 0)              := x"00";
variable B  : std_logic_vector(7 downto 0)              := x"00";
variable X_16_bit   : std_logic_vector(15 downto 0)             := x"0000";

begin

                  ------------------------
***THE CODE THAT calculates X_16_bit at every 0.5 seconds*** 
                   -----------------------

//SPLITTING code runs in 50MhZ clocked process 

UPDATED

        X_16_bit := x"4563";
        IF(x = '0') THEN     
            A := X_16_bit (15 downto 8);                        
            B := X_16_bit (7 downto 0);
            tx_data <= A;   
            x := '1';

        ELSIF(x = '1') THEN 
            tx_data <= B;                       
            x := '0';
        END IF;
end process;

UPDATED
with this code i get only 63 on tx output. i dont get 45 at all.