Electrical – How to convert a Karnaugh map into a Logic gate circuit

logic-gates

Ok, so I currently have some questions that I need to work out in uni, I've basically been given 2 lengthy boolean expressions and I need to simplify them.

Question a I feel like ive done right but question b im stuck on as its so long and im fairly new to Logic Gates still. Ill attach a picture of the question and what ive come up with so far for the karnaugh map,

I feel like I understand how the terms work and how to get them with say ABC = 2 terms, AB = 3 A =4 etc. I know that the + symbols are OR gates.

Added another image below, I knew about being able to overlap when circling the inputs but didnt know and still have no idea what they mean or how to replicate those circled inputs into a logic gate circuit, ill have to do some research on karnaugh maps. Also apologies for the mistype earlier, I put AND instead of OR.

Id assume the 4 shown below would replicate the 4×1 4×1 4×1 and 2×1 inputs but id assume i have to change quite a few things

My attempt at creating the circuit:

Best Answer

After an update to your question you came up with

Here's the same equation you wrote but with "Y=" added to it for clarity:
\$Y = \bar{A}\bar{D}+\bar{A}B+\bar{A}C+\bar{B}C\bar{D}\$

The equation is correct.

How do I convert a Karnaugh map into a Logic gate circuit?

Now, look at what the equation actually say,
it says that \$Y\$ is equal to \$\bar{A}\$ AND \$\bar{D}\$ OR \$\bar{A}\$ AND \$B\$ OR \$\bar{A}\$ AND \$C\$ OR \$\bar{B}\$ AND \$C\$ AND \$\bar{D}\$

So let's just make that logic circuit three times in three different ways.

Link to simulation.

Top left is the naive solution that implements the function blindly
Top right is when you move the logical NOT gates backwards and join them
Bottom is when you factorize \$\bar{A}\bar{D}+\bar{A}B+\bar{A}C\$ into \$\bar{A}(\bar{D}+B+C)\$

All 3 of them give the same output as the karnaugh map. All 3 of them are viable. If you have many NAND or NOR gates laying around then you can apply De Morgan's law and then you have a solution that uses NAND and NOR heavily and you can use up some NAND and NOR gates.

The correct logic circuit for you boils down to what you are allowed to use or some other requirements/constraints on your project. Keep in mind that NAND and NOR gates usually requires fewer transistors to implement and are therefor usually the gates you want to use.

Related Solutions

Electronic – Karnaugh Map from this expression

Your K-Map is correct.

R = (X + X' + Y' + Z)(XY + X'Y'Z+YZ')

R = (1 + Y' + Z)(XY + X'Y'Z+YZ')

R = (1)(XY + X'Y'Z+YZ')

R = XY + X'Y'Z+YZ'

R = XYZ' + XYZ + X'Y'Z + XYZ' + X'YZ'

R = XYZ + X'Y'Z + XYZ' + X'YZ'

respective terms of last equation will be logic one in K-Map

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

Do I combine all of the expressions (as in W+X+Y+Z or WXYZ)

No. What the equations show you are how to derive outputs for four separate pins. If you wanted to combine the four pins you should have done it earlier when coming up with the Karnaugh map (the Karnaugh map would then only have one output instead of four).

First step, treat the four as four separate circuits:

A ─┬───────────────┐
   │               │
B ──┬─[NOT]────────[AND]┐
   ││              │    │
C ────[NOT]──┬─────┘    [OR]── W
   ││        └[OR]─┐    │
D ────────────┘    │    │
   │└──────────────[AND]┘
   └──[NOT]────────┘

 .... implementation of other circuits left as homework

A ──[NOT]────────┐
                 │
B ──[NOT]──┐     [OR]─┐
           [AND]─┘    │
C ──[NOT]──┘          [AND]── Z
                      │
D ────────────────────┘

Second step, join A to A, B to B etc.. This is obvious because obviously A is the same as A etc.

A ─┬────┬───────────────┐
   │    │               │
B ──┬────┬─[NOT]────────[AND]┐
   ││   ││              │    │
C ───┬─────[NOT]──┬─────┘    [OR]── W
   │││  ││        └[OR]─┐    │
D ────┬────────────┘    │    │
   ││││ │└──────────────[AND]┘
   ││││ └──[NOT]────────┘
   ││││
   └───────[NOT]────────┐
    │││                 │
    └──────[NOT]──┐     [OR]─┐
     ││           [AND]─┘    │
     └─────[NOT]──┘          [AND]─ Z
      │                      │
      └──────────────────────┘

 .... implementation of other circuits left as homework

The circuit should be working at this point but if you're paying attention you may notice that some parts of the W and Z circuits are sharing the same logic. For example, we're using NOT on B and C twice. The next (optional) step is to refactor the circuit and remove redundant/repeated subcircuits and components:

A ───┬──────────────────┐
     │                  │
B ────┬─[NOT]──┬────────[AND]┐
     ││        │        │    │
C ──────[NOT]───┬──┬────┘    [OR]── W
     ││        ││  │         │
     ││        ││  [OR]─┐    │
D ─┬───────────────┘    │    │
   │ ││        ││       │    │
   │ │└─────────────────[AND]┘
   │ │         ││       │
   │ └──[NOT]─┬─────────┘
   │          │││
   │          └─────────┐
   │           │└─┐     [OR]─┐
   │           │  [AND]─┘    │
   │           └──┘          [AND]─ Z
   └─────────────────────────┘

 .... implementation of other circuits left as homework

Best Answer

Related Solutions

Electronic – Karnaugh Map from this expression

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

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