Electrical – How to divide complex number in VHDL

arithmetic-divisionvhdlxilinx

I know how to divide numbers in VHDL (or using one of the Xilinx IP core generators) but I do not know how to do it in the case the numbers are complex.

In my case I have defined a complex number as this:

type complex12 is record
    re  : std_logic_vector (11 downto 0);
    im  : std_logic_vector (11 downto 0);
end record;

So my complex number it is just two vectors of 12 bits, one for the real part an other for the imaginary part.

Let say that now I have a and b complex numbers:

signal A : complex12 := (re => (others=>'0'), im => (others=>'0'));
signal B : complex12 := (re => (others=>'0'), im => (others=>'0'));

I know that the theory for dividing to complex numbers tell us two approaches for doing a division:

$$
c = \frac{a_r + j\cdot a_i}{b_r + j\cdot b_i} = \frac{(a_r + j\cdot a_i) \cdot (b_r – j\cdot b_i)}{b_r^2 + b_i^2}
$$

Alternatively:
$$
c = \frac{|a|}{|b|} \cdot e^{j (\angle a – \angle b)}
$$

But both approaches seem very difficult to implement in VHDL. What would be the preferred approach? Is there an easy way to divide complex numbers? Is there any Xilinx block that can save the day? I am bit lost on how to approach this.

Best Answer

You've got the right idea with that first equation. You've just got to do some more algebra:

$$ c = \frac{a_r + j a_i}{b_r + j b_i} = \frac{(a_r + j a_i) (b_r - j b_i)}{b_r^2 + b_i^2} $$

$$ c = \frac{a_r b_r + a_i b_i + j a_i b_r - j a_r b_i}{b_r^2 + b_i^2} $$

$$ c = \frac{(a_r b_r + a_i b_i) + j (a_i b_r - a_r b_i)}{b_r^2 + b_i^2} $$

$$ c = \frac{a_r b_r + a_i b_i}{b_r^2 + b_i^2} + j \frac{a_i b_r - a_r b_i}{b_r^2 + b_i^2} $$

Yes, there are a lot of operations required. Looks like 6 multiplies, two additions, one subtraction, and two divisions. Yes, implementing this in Verilog/VHDL will be rather complex. If you don't need maximum throughput, then you can probably get away with one multiplier and one divider and then sequence the operations with a state machine. Compute the denominator first, store it, then do the numerators, computing the second one while the divider is working on the real part of the output.

Related Solutions

Electronic – Multiplication in VHDL

If you multiply 2 5-bit numbers (A and B are both std_logic_vector(4 downto 0)) don't you need 10 bits (not 9) to store it in (so P should be std_logic_vector(9 downto 0)? (31*31 = 961: needs 10 bits)

But also - don't use std_logic_arith/_unsigned. Use ieee.numeric_std and then use the unsigned data type.

How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA

Basically, there are two ways of doing this. The first is to use the Xilinx native clock synthesizer core. One of the advantages of this is that the Xlinx tools will recognise the clock as such and route it through the required pathways. The tools will also handle any timing constraints (not really applicable in this case, since it's a 2Hz clock)

The second way is to use a counter to count the number of faster clock pulses until half of your slower clock period has passed. For example, for your case, the number of fast clock pulses that make up one clock period of a slow clock cycle is 50000000/2 = 25000000. Since we want half a clock period, that's 25000000/2 = 12500000 for each half-cycle. (the duration of each high or low).

Here's what it looks like in VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;

entity scale_clock is
  port (
    clk_50Mhz : in  std_logic;
    rst       : in  std_logic;
    clk_2Hz   : out std_logic);
end scale_clock;

architecture Behavioral of scale_clock is

  signal prescaler : unsigned(23 downto 0);
  signal clk_2Hz_i : std_logic;
begin

  gen_clk : process (clk_50Mhz, rst)
  begin  -- process gen_clk
    if rst = '1' then
      clk_2Hz_i   <= '0';
      prescaler   <= (others => '0');
    elsif rising_edge(clk_50Mhz) then   -- rising clock edge
      if prescaler = X"BEBC20" then     -- 12 500 000 in hex
        prescaler   <= (others => '0');
        clk_2Hz_i   <= not clk_2Hz_i;
      else
        prescaler <= prescaler + "1";
      end if;
    end if;
  end process gen_clk;

clk_2Hz <= clk_2Hz_i;

end Behavioral;

Things to note:

The generated clock is zero during reset. This is ok for some applications, and not for others, it just depends what you need the clock for.
The generated clock is going to be routed as a normal signal by the Xilinx synthesis tools.
2Hz is very slow. Simulating for a second is going to take a while. It's a small amount of code, so it should be relatively quick to simulate even for 1 second, but if you start adding code, the time taken to simulate a clock cycle of 2 Hz could be significantly long.

EDIT: clk_2Hz_i is used to buffer the output signal. VHDL doesn't like to use a signal on the right of an assignment when it is also an output.

Best Answer

Related Solutions

Electronic – Multiplication in VHDL

How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA

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