This looks like a homework question, which I won't answer. But here are some pointers:
You cannot represent more states than what you have available -> that means that you will have to go to the next higher state (i.e. 2 FF's for 4 states) or use only one FF per state. (i.e. FF #1 correlates directly to A).
option #1 ( 2 FF's and 4 states) is more economical but you have to make sure that the unused state does n't not get activated and then locks out.
- you might draw this as a 4th state "D" with loops back to itself.
- what is generally considered safe design is that you always have explicit transitions AWAY from the unused state in case it gets activated.
option #2 uses more FF's but cannot have any hidden states.
- it is inherently safer.
- it is known as a "one hot" design and thermometer codes are examples of this.
Your choice of states "A = 00" etc. will make the design simpler or more complicated. SO may want to go with what you decribe or you may want to go with state C = "10". You should look at all possibilities.
The first SM, only uses 0 or 1 as an input because it only has one input variable. They should have used a variable for clarity anyways. You'll notice in the table that it is marked as "x" but not in the diagram.
Based on your state diagram and explanation, you have everything you need there.
For every register (you have 4), you need to create a Karnaugh Map which determines what value will be clocked onto that register in each clock cycle.
The next value for each state register will depend on the current state as a whole (i.e. all state registers), and any other inputs (in your case only reset). So build your Karnaugh Map using those inputs.
Each of your states has a 4-bit value (e.g. your starting state is 1101). So you will need 4 registers to hold the value indicating current state. So for example lets call your state registers \$\left(S_3, S_2, S_1, S_0\right)\$, where the starting state would be say \$S_3=1\$, \$S_2=1\$, \$S_1=0\$, and \$S_0=1\$. Also lets call the reset signal \$R\$.
You will have maps which look something like:
$$
\begin{array}{c c c| cc}
S_0 & & R & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1\\
& & S_3 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0\\
& & S_2 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0\\
S_0 & S_1 & \\
\hline
0 & 0 & & & & & & 1 & 1 & 1 & 1\\
0 & 1 & & 1 & & & & 1 & 1 & 1 & 1 \\
1 & 1 & & 0 & 1 & & 1 & 1 & 1 & 1 & 1 \\
1 & 0 & & & 1 & 1 & & 1 & 1 & 1 & 1 \\
\end{array}
$$
I've been exceedingly nice and filled in the map for \$S_0\$ for you based on your next state table. I'll let you make and fill in the other three maps.
Once you have your four maps you know the logic for each of the state registers.
Best Answer
Just like writing computer programs, good descriptive choice of variable names helps. Nobody would use 'a' as a variable name in code these days (I hope, or if they did, wouldn't expect to understand it a month later), they'd tend to use 'cars_per_hour', or 'creation_date', something meaningful.
Likewise for state machines. It's much easier to 'play computer' if we have meaningful state labels.
The task is to spot three consecutive 0s. How do we do that? We spot a single zero three times, and remember where we are in the process. How do we remember? For this question we are asked to use a state machine.
Let's have a state 'no_zeroes_seen_yet'. We start in that state, and go to it any time we see a '1'. Another state would be 'one_zero_seen'. We move to that state if we are in 'no_zeroes_seen_yet' AND we see a '0'. Another state would be 'two_zeroes_seen'. How do we get there?
Relabel the 'a', 'b' and 'c' states of the suggested answer with these more meaningful labels, and see if that helps.
I notice the answer leaps on to code these three states with A and B binary bits, which I feel is a bit premature. I would never conflate these steps, first getting to a pure logical FSM diagram, and then handling the implementation later (just like premature optimisation militates against clear code!).
FWIW, a 'one-hot' implementation is far easier to deal with, maps better onto VHDL and code, but is uses more D-flops. Again, similar arguments contrasting clarity and 'efficiency' are raised for and against compilers!
Do we have a 'three_zeroes_seen' state, or do we rely on 'two_zeroes_seen' AND another '0' to mean the same thing? That's the difference between Mealy and Moore styles, it's important to know which style is required. The suggested answer appears to assume Mealy without comment. Mealy tends to be smaller and more 'efficient'. Try reading about 'Mealy machine' on wikipedia.
Re-reading the question, the 'minimal' word is directing you to use a binary-coded Mealy machine, though I would still design it behavioural first, implementation second.