Electrical – How to find out if a binary number is zero or not using logic gates

There's simply no way around ORing all the bits, as unsatisfying as that may seem. However, you are not restricted to two input gates in silicon either. You can build a 4-input NOR gate in CMOS logic by putting 4 series p-type transistors in the pullup network and 4 parallel n-type transistors in the pulldown network. That reduces the depth of your tree topology and therefore your propagation delay. You can only take that theory so far though before the cumulative voltage drop across the series transistors makes the pull-up not pull-up enough to be a "1"... four is a good rule of thumb if I remember correctly.

I would probably use two bits to encode the three switches, and the general approach would be to have a string of pairs (one for each bit) of D or JK flip-flops to accept the sequence of input digits, essentially a shift register for pairs of bits. Then there would have to be de-bounce circuitry for the switches, and some way to generate a clock signal from the key presses (probably on release) to shift the digits through the register. Finally, XOR gates between the stages of the shift register and the digits of the key (hardwired to 1231 or use switches, etc) would produce signals to indicate when each digit is a correct match (logic Low on match), and then a multi-input NOR of the XOR outputs would give a final output signal that would indicate when the entire sequence in the shift register matches the key.