Electrical – I’m writing a simple verilog code, having little trouble

Two problems:

1. You need to wrap an always block around your combinational logic. Something like always @* begin

then put your if statement in there.

2. You can't assign a wire inside an always block. you need a reg.

You must not include another module within the module/endmodule keywords. I no longer get errors when I make the following changes:

task_calling.v:

`include "ANDgate.v"

module task_calling();

`include "simple_task.v"
  reg tb_a;
  reg tb_b;
  wire tb_c;  

ANDgate myAND (
  .a(tb_a),
  .b(tb_b),
  .c(tb_c));

initial
  begin 
    task_ANDinputs(tb_a, tb_b);
    $display ("time = ", $time, " a = %d, b=%d, c=%d", tb_a, tb_b, tb_c);
  end  

endmodule

simple_task.v:

task task_ANDinputs(output x, output y);

begin
  x = 1'b1;
  y = 1'b0;
end

endtask

I changed your always to an initial to avoid an infinite loop.