Electrical – Intel iGPU die area and power consumption

I can help to address the first part of your question. As an abstraction of a single switching device inside a processor, imagine a MOSFET connected to ground with a load resistor to the power supply (in a real CMOS part there wouldn't be a load resistor, but another transistor, but this distinction is not important for the analysis). Connected from the junction of the resistor and the transistor is a capacitor, representing all the input capacitances of the transistor that the transistor under discussion is driving. When the first transistor switches off, this capacitance will be charged up through the load resistor. When the first transistor switches back on, the charge stored on the capacitor will be discharged through the first transistor.

It can be shown that when a capacitor is charged through a load resistor, 1/2 of the energy used in charging the capacitor is lost in the resistor, for a total energy dissipation of \$\frac{1}{2}C{V_s}^2\$, where \$V_s\$ is the supply voltage. When the switch then turns on, assuming the resistance of the switch is much less than the load resistance, that same energy will be dissipated in the switch, for a total energy of \$C{V_s}^2\$. Dividing this by the switching period gives you the dynamic power dissipation of the switch/capacitance combo, \$C{V_s}^2f\$. Shrinking the die reduces the junction capacitances of the MOSFETS, so if you know the supply voltage, switching frequency, number of transistors and the approximate junction capacitances of a certain process, you could calculate a ballpark figure of what kind of power savings a process shrink entails, all other things being equal.

Intel CPUs have the cost directly dependent to size of cache. The amount of die devoted to L1-L2-L3 cache can be as large as 50% or more. So the elementary block for the cache is multiport single bit SRAM cell with write-through/read through path. It can comprise may be dozens of transistors per bit of memory. And how it looks in schematics is possibly a trade secret.

Effectively everyone who buys contemporary CPUs pays mostly for this cache structures, as they consume most of die real estate. Intel and other CPU manufacturers are mostly in business of selling very large raw caches sprinkled with few CPU/FPU cores here and there. There are even DRAM bga solutions which can be soldered as stackable tier on top of CPU chips. One more evolutionary step and all large cpus will start directly compete with DRAM industry.