Electrical – Is it possible to load values to a counter upon startup

counterdigital-logiclogic-gates

I'm designing a digital clock for a freshman electrical engineering projects course. I am using SN74HC161 4-bit synchronous counter chips for the counting. My design counts seconds and minutes with correct rollovers, and I am going to design the hour logic next.

I am wondering if it is even possible to load values onto my counters as soon as the clock powers up. My counter begins from zero, but I want the clock to default to midnight, for example, because 0 o'clock does not exist. Though I will be adding a feature to set the clock's time (by manually incrementing hours), I don't want my clock to start off with zeros across all my seven segment displays.

This low-res picture is just for a general idea of my design. I am using NI Multisim (and yes, I understand this is a noob-ish piece of software, but I am a freshman electrical engineering student).

Here is a closeup of my counter / decoder chips so you can makeout the pinout.

Any help would be greatly appreciated.

Best Answer

I'm having trouble seeing the pins on your parts, but I believe I see a 'clear' or 'reset' input. If you place an RC circuit that goes into a Schmitt trigger and run the Schmitt trigger into your clear outputs, then at power up, the resets will all be held until the RC charges, typically a few milliseconds.

Looks like fun!

Edited to add a schematic using a comparator instead of a dedicated Schmitt trigger. Same idea. Set the delay using R1 and C1. Set the threshold using R2 and R3. If you need to invert, then keep R4 where it is and reverse the voltage divider and the RC circuit.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Related Solutions

Electronic – CPLD best practice for resetting a counter

It sounds like you don't have an external reset signal to respond to, you just want to count to some number then go to zero as the next step. You could consider this a mod n counter, where n is one more than the maximum count in your counter.

So I'm not sure what you mean about "losing a signal" while doing the reset. If you had a 3-digit decimal counter and it rolled over from 999 to 000, you wouldn't consider it as "losing a signal", it would just be counting to the next value in mod-1000 arithmetic.

So if you do

always @(posedge clock) begin
    if (counter == some_number) begin
         counter <= 0;
    end
    else begin
        counter <= counter + 1;
    end
end

You'll have a counter that counts continuously in mod-some_number+1 arithmetic. Alternately you could say it counts to some_number, then resets to zero without ever "losing" a clock pulse.

If some_number+1 happens to be a power of 2, you don't even need the reset condition in your code. For example, for a mod-16 counter, you can just use a 4-bit counter, and the synthesized logic will count continuously and repeatedly from 0 to 15.

Electronic – Any sequence asynchronous counter

Asynchronous means you don't have a clock signal to control the counter. There is no arbiter that will tell you when the outputs are valid. This implies that subsequent stages cannot tolerate any glitches in the counter. This in turn means you want only a single bit to change between two counts. For every current combination of output levels, you can uniquely identify the next step.

In Dutch it is called a univariante code, I don't know the proper English translation for it, but means that between every step only a single bit will change. Wikipedia writes: "two successive values differ in only one bit". Gray code is a well known example for this. As at every moment only a single bit will change, you still get a stable counter which runs at the maximum speed of the silicon. It also means you cannot use just any arbitrary sequence you like.

If you want an arbitrary sequence, you can use output logic for your outputs but you will get glitches: illegal temporary values caused by difference in port propagation delay.

A sequence like this is easy to design using a Karnaugh map. Just make a loop without interruptions of your desired length. Here is an example 12 stage code I just made up.

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Best Answer

Related Solutions

Electronic – CPLD best practice for resetting a counter

Electronic – Any sequence asynchronous counter

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