Electrical – JTAG, OpenOCD and Atmel SAM3X

The typical thing to do on Cortex parts that only have a single processor core is to only use SWD. In this case, the only lines which need to be routed to the 10-pin header are SWDCLK/SWDIO/SWO/!RESET/+3V3/GND. Notice that !RESET is the microcontroller reset, and is not the same as TRST. From my experience, the only pin that needs to be pulled up via a resistor is !RESET, at least using a Ulink2/Ulink ME debug adapter. On most Cortex processors, the JTAG and SWD lines are actually shared, for example, SWO is the same pin as TDO, but that appears to not be the case here. If your tools support both JTAG and SWD, you can pick the system which conflicts the least with your other peripheral/pinning needs. If you must share the debug pins with other hardware, then the ISP pin should be pulled up and wired to one of the GND pins on the 10 pin connector (the GND pins are internally shorted on the debug adapter so that it will pull down when the debugger is connected, allowing you to enter ISP mode).

In general, SWD requires fewer pins, and can use SWV (Serial Wire Viewer) which gives you printf redirection and other features, while JTAG allows for chaining (and access to both cores on dual core parts such as the LPC4300), and is the only option for older tools.

The part number for the shrouded connector is FTSH-105-01-F-D-K, but in practice it is difficult to find, but you can probably put out a RFQ on Alibaba or a similar B2B site.

Taken from a Segger web page:

1 VTref Input This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.

2 Not connected NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

3 nTRST Output JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unin- tentional resets when there is no connection.

5 TDI Output JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.

7 TMS Output JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of target CPU.

9 TCK Output JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.

11 RTCK Input Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.

13 TDO Input JTAG data output from target CPU. Typically connected to TDO of target CPU.

15 RESET I/O Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".

17 DBGRQ NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.

19 5V-Target supply Output This pin can be used to supply power to the target hardware.