Electrical – Lattice Machxo3 FPGA configuration using I2C

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I have a Lattice Machxo3 FPGA based design / board and currently I am configuring the FPGA using JTAG. As per the datasheet I2C also can used as the FPGA configuration interface. Is it possible to use the I2C as the primary interface to configure instead of JTAG? The datasheet mentions that I2C can be used for reconfiguration. I just want to confirm.

Also, is there any same code available wishbone interfacing to configure FPGA?

Best Answer

Yes it is possible to use I2C for configuration. Almost all of my project are using the I2C interface only because of the reduced required pin count. Drawback is that one has to be more careful to not brick a device because recovery can be impossible without the JTAG interface.

required steps:

making sure that I2C is enabled in the Feature Row Editor
setup the EBR block (e.g. via IPExpress)
instance the EBR block in your design and make sure to route a proper clk to it (I recommend to use the internal oscilator OSCH)
connect a I2C "master" to your device (make sure to have pull ups for SDA and SCL in place. Typically I use a FT2232H mini module, which is recognized by the lattice diamond programmer as regular programmer)
setup programmer software to verify the device code via I2C to check for proper connection
setup programmer software to write feature row via I2C with 10000(00) as address
setup programmer software to verify the device code via I2C to check if the device is still responsive
now one can set the regular I2C erase, write, verify mode for programming

Additionally I recommend to assign individual I2C addresses for every pinout / board vision. Else it can happen that one program a device which an bitstream which is not pin compatible. This is especially a thing if you route some of the connections over other pins (which I frequently do to avoid the way more expensive via-in-pad technology).

Using the I2C interface not only for configuration but actively as interface is a different beast imho. I have some code for purely receiving mode via the wishbone EBR interface that can be extended to support writing as well which I might add later if there is any interest.

P.S. a few additional information can be found here: http://buildingelectronics.blogspot.com/2017/09/machxo3lf-tips-tricks.html

P.P.S: avoid to connect any outputs to the system pins as this might hinder the programming of a blank device via I2C. E.g. do not drive the SN pin with an external circuit as this might enable the SPI interface blocking of the I2C interface.

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Electronic – Is it possible for an FPGA to “partially” configure

It's not really possible for the FPGA to exit the start up routine with a corrupted configuration as it confirms the CRC of the configuration after the complete configuration is loaded, but before it tries to start up. If it does not match, then the DONE pin stays low and you can check on what happened by reading the status bits over JTAG.

Since it seems like the configuration is always completing with the DONE pin released and your divided clock output is working, my guess is you may have a metastability issue or initialization issue in your design that you haven't caught yet.

Electronic – Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)

Answering my own question here, as it turns out you are NOT supposed to use clock dividers in VHDL. I had falsely assumed this was fine as long as you treated each clock as a clock, however as it turns out there is a single hardware specific route that the clock takes, and a second clock sourced from a divider simply does not have the same small-delay properties of the custom clock line.

I got all this from this forum post (edaboard.com/thread283723.html), in which they recommend replacing clock dividers with clock enablers. So rather than having all your logic triggered by a clock edge, you have a clock edge trigger a look at a conditional, which looks to see if "clock enable" is high, and if it's high then it runs the code. As long as you keep clock enable high for just one clock cycle, then it acts the same. You just basically turn it high every 10 million cycles and low on the 10000001th, if you want a clock divided by 10 million for example.

You want to avoid going

if(clk = '1' and clock'event and clock_enable)

as I'm fairly certain you're supposed to avoid logical operations with your clock (I'm new to VHDL so I've never experienced this myself, just read it in other forum posts). Instead you go

if (clk = '1' and clock'event) then
    if (clock_enable = '1') then
    ...

Best Answer

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Electronic – Is it possible for an FPGA to “partially” configure

Electronic – Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)

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