Electrical – Low-frequency response of a CS amplifier

The negative and positive overshoots you see in the actual waveform are probably resulting from how you have the circuit wired up. If you have long jumper wires and a poor grounding system this can lead to that behavior.

As far as to why the output rise time is so much slower than in reality than in the simulation - this is mostly due to the capacitance of the drain node in the circuit. This capacitance comes in part from the components themselves but may also be largely attributed to the way the circuit is built. For example if you have long leads and are using a pluggable type proto-board you will have more capacitance than if you built the circuit onto a real circuit board.

One way to evaluate just how much capacitance may exist on the drain node of your circuit is to go back to your simulation and add a capacitor from the drain to GND. Then iteratively adjust the capacitor value and rerun the simulation till the waveform starts to look much more similar to what you measured in the actual circuit.

You can substantially reduce the effect of the drain node capacitance by lowering the 200K / 100K resistors in your voltage divider to say 20K / 10K or even 2K / 1K.

The Vgs shown in the drawing is not inline with the first equation.

Vout = Itotal*Rs

Itotal = VgssCgs + VgsGm

Vout=Vgs*(sCgs+Gm)*Rs

Vout/Vgs = Rs*(sCgs+Gm)

Cds and Cgd neglected.