Electrical – Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

cmosflipfloprtlvlsi

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has positive clock, like this:
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On the other hand, "usual" master slave flops have master on positive clock and slave on the negative clock, meaning they sample D on posedge and update their Q on negedge, like this one:
enter image description here

Question: why such flops are not the default flops that are used? Most CMOS libraries and designs are using posedge flops.

But, there are several advantages to master-flip flops that update their Q on negedge:
1. No headaches with hold timings, as D won't trigger on the posedge together with clock, making timing analysis simpler
2. No simulation shoot-through. If your design has clocking path longer than D path (for instance, there are clock gates), then the next stage will properly sample "previous" D value, instead of "currently updated" new one.
The only disadvantage I see is that you lose half a period of time for your combinational logic to settle.
Is there something else that I am missing?

Best Answer

You are correct that master slave flip-flops provide the nice functionality that you define.

However there are other situations where you need that first latch on it's own.

For example, where the output of the second latch is dependent on some other input..

schematic

simulate this circuit – Schematic created using CircuitLab

As such you need the simple edge triggered latch as the primitive.