clockflipflop
This is the all question.
I thought that because Tcq>Th we will only count Tcq. If we need to know the minimum clock period, we should calculate the duration from the beginning to the output of DFF1. It makes TpdX+Tsu+Tcq+TpdA+TpdX+Tsu+Tcq = 51ns. Is that right?
I didn't get how the minimum clock period will occur when there are 2 flip flops. Because second flip flop depends on output of the first flip flop. Will we count Tcq twice?
If you scrutinize the data sheet for a real D-FF carefully, you will see an item called 'setup time'. In actuality, the FF doesn't grab the value at the exact time of the clock edge; the data has to be stable for the last 20 ns or so before the clock rises, and that's the value that gets transferred. Also, the value at the output takes a few ns to settle down to the (possibly) changed value. So if you daisy chain a string of D-FF's together, Q from one into the D of the next, everything works because during the critical time for each stage's D input, the Q's are stable; the Q's only change very shortly after the active clock edge.
From my textbook, Digital Design and Computer Architecture, Harris and Harris, pg. 88
An important note
When you are attempting to find the propagation delay of a combinational circuit with multiple elements, you must add the propagation delay through the critical path.
However when you are attempting to find the contamination delay of a combinational circuit with multiple elements, you must add the contamination delay through the shortest path.
That much is probably obvious to you.
Actually, it sounds to me like you are referring to contamination delay. You said contamination delay is the amount of time measured after an input changes that the output remains valid. If you mean the previous output, then yes, because that means the same thing as until the output begins changing to the new value.
Addition
About your question as to how this deals with reading and writing from a register. This confused me for awhile, but I think it makes perfect sense to me now.
So what you said about contamination delay and hold time is correct. This problem applies to when flip-flops are daisy chained. And if you think about it, it also only applies to when you want to read and write at the same time.
Imagine a circuit with just 2 flip flops. It doesn't necessarily have to be a register, just that the first flip-flop is the storage element that is written to, and the 2nd flip-flop is the storage element that reads the first one. If you only needed to read and write on different clock cycles, then none of this delay stuff would matter, because reading would always occur on a different clock cycle when the output of the first was stable, and couldn't change since writing can't occur in the same clock cycle.
However if you wanted to write a new value to the 1st flip-flop, as well as read the previous value properly into the 2nd on the same clock cycle, then that is the exact situation you described, where if the contamination delay of the first was less than the hold time of the second, then writing to the first would thereby contaminate the reading of the second. It makes perfect sense. The read has to occur successfully before the write begins to change what's being read, or else the value gets lost.
Best Answer
No. Your reference points are the rising edges of the clock signal. Everything starts and ends there.
Therefore, to calculate the minimum clock period, you start with the Tcq of any FF, add all of the logic delays leading to the input of any other FF (including itself), and add Tsu last. Use the maximum values of each delay for this calculation. In this circuit, there are three separate paths you need to consider.
Then, you go back and add up the minimum delay values (sometimes called "contamination delay" in modern texts) to verify that Th is also met on every FF.