fpgapowerxilinx
I am trying to find power consumption of my vhdl code.I am going to use the power estimator in xilinx 9.2.Do the power analysis results vary in xilinx 9.2 and xilinx 14.7??
Also will xilinx provide accurate power analysis results ??
Is there any other tool to find acccurate power consumption of vhdl code??
I'm not familiar with VHDL, but it seems to be doing this: output Deb_Sig is 1 only when input Sig has been 0->1->1 (time grows to the right), sampled at the rising edges of CLK. Otherwise, Deb_Sig is 0. So, the module detects rising edges at the input, and only those ones that are followed by a high level that, after sampling, turns into at least two logic 1 samples. That way, it will ignore pulses that are high during only one sampling instant, which will be considered noise.
I would say that your code synthesizes something equivalent to this:
Curiously enough, it may ignore high pulses that last 2T-epsilon (where T is the sampling period), and detect high pulses that last T+epsilon (which is shorter than 2T-epsilon), if the sampling is such that it sees only one logic 1 in the former pulse, but two logic 1s in the latter one.
The reason they direct you to a power estimation tool is because the power consumed depends very heavily on how hard the device is working.
Intel know that their processors will be clocked at the max rated frequency (at least some of the time) and that all the processing units will be used (at least some of the time).
Xilinx have no idea what their customers will do. It may be that the design is slightly too big for a small device, so needs the larger device, hence only (for example) 60% of it is used and the other 40% lies idle, not consuming dynamic power. Most time customers cannot clock the entire device at anything close to the theoretical fmax, so that reduces dyanamic power also.
If you were to calculate a theoretical max power dissipation, it wouldn't help much as you'd then end up overspecifying your power and cooling subsystems by a factor of (guessing) 2x to 4x!
Best Answer
Normaly there are some spreadsheets supplied by your FPGA maker to estimate the power compsuption based on clock speed and resource usage. I never managed to get them to work thought :)
i suggest you get your VHDL code synthetised , and then make it run in a dev board (same FPGA model & speedgrade), then measure the consumption of your "code".
this will give you an estimate, remember , always apply a tolerance factor to your results.