The results shown in the Bode plot are reasonable, and likely accurate.
Here is the Bode response I got with a quick level 1 opamp model of the OPA3355.
It shows slightly higher Q than your result, but I put no effort into the output impedance of the opamp model. A more realistic model would lower the Q.
R1 and C1 combine to form a zero at about 120kHz, causing the gain to start rising there. Gain continues to go up at 20dB/decade as expected until it collides with the gain bandwidth limit of the OPA3355 (which only has a gain of 20dB at 10MHz). The pole and zero interact in an active way that shows up as a high Q gain reversal. This is usually considered a bad thing, to be avoided. The virtual ground relationship falls apart where the zero and bandwidth limit interact since there is no gain to make it work.
Edit: Why this might be a problem.
Two main applications for opamps are in control loops for stability and as active filters for signal processing. Both of these areas need precise placement of zeros and poles, and control of gain. None of these features can be controlled with the opamps raw parameters, but must be improved with feedback. Once raw opamp gain exceeds application gain by less than about 20dB, benefits of feedback break down and the amplifier may not respond as expected. Without proper feedback margins the amplifier response could be nonlinear and unstable.
In this case for example, location of the response peak relies on the raw open loop gain. Open loop gain can easily vary by 10dB over different conditions and units (opamps). Typical open loop gain for the OPA3355 is 92dB with a minimum of 80dB. So, one would have to consider what impact that 10+dB variation would have in the location of the peak (in gain and frequency). Most applications would have more strict requirements than those sorts of variation would allow. None of this is to say that adding 20dB or so of gain in an amplifier response is wrong. In fact, it is commonplace to have zeros place to boost gain. But these are done with proper allowance for gain margins, and the effects of such zeros is removed by placed poles at higher frequencies to meet gain allowance. For this circuit a gain boost of about 15dB could be managed with enough gain margin by adding two poles to cap the effect of the zero. One of the poles is already there by R2 and C1 (you don't see it because the frequency is too high). A second pole could be added with a small capacitor in parallel with R1. These poles would need to roll amplifier gain off to 0dB by about 10MHz.
It is possible that the low frequency gain of -6dB is a result of source impedance of 52 Ohms for Vin with a shunt resistance of 52 Ohms (R5)
Assuming your Device Under Test (or DUT) and total wiring are sufficiently lossless this might work well enough.
Your basic maths steps are all in order, the power dissipation in the resistors should be fine if they are all within 25% of each other in value, which you can usually assume if they are the same type. If it says a margin on it, like 5%, you can use that to check for certainty.
If your DUT, however is very lossless when "turned on", limiting the current through the supply at 30A will not prevent a higher peak from going through. Your supply has capacitors on its output, so if at 30A your device is supposed to waste near enough to 0V (supposed to, versus what it ends up being is of course a factor in this), it will very shortly dump the full 15V with maximum current through your DUT.
Whether that is a microsecond or a milisecond is down to your lab supply, but you should then assume a peak current of:
\$I = \frac{V}{R} = \frac{15V}{0.3333...Ohm} =~ 45A \$
during that time, until the capacitors are empty (EDIT: Not empty, of course, but settled to the new voltage of 10V needed for 30A) and the regulation of the power supply balances out at 30A.
The resistors will not mind this at all, firstly because they are very large, bulky, 225W things, so even 45A continuous would be fine (if they are within 1% in value, at 225W things can quickly escalate into poof). But also because of their mass they can easily handle very short spikes a bit above their handling capability, as long as you then settle below their maximum power.
Whether your device will like it: That only you know.
Best Answer
So the first thing is to decide on an accuracy on the current that one can live with, as this sets other parameters. So lets say 0.03A, or 1% of full scale.
Next, let's define the process we want to control as the circuit from Vgate(Vfet in the schematic) through U4-output. Lets call that Vout. Checking the fet datasheet, the gain given is 13 A/V, although perhaps less depending on actual bias point in the application. Sense resistor 0.01ohm. INA168 setup for 75V/V gain. U4 unity buffer. Total process DC gain 13*0.01*75*1 = roughly 10 V/V.
And the error at Vout will be 22.5mV for a 30 mA current error.
The input at Vgate will be somewhere in the 2-10 V range, say nominally 5 V. Vgate-nominal / Vout-errorlimit roughly equal to total open-loop gain for appreciable gain >> 1. So minimum open loop gain required about 5V/.0225V = 222 V/V. The "process" provides a gain of about 10 V/V above, so control loop gain minimum about 22.
The control circuit above (from Vout, aka U4-output) to Vgate has 4.7 V/V gain at frequencies above 3.4kHz, and unlimited gain at DC, well limited only by the internal gain of U7, which could be 1000V/V or more. That may be super accurate in terms of output error, sort of, but can be challenging for stability. If one is using 1% resistors, then there is already 1% error at R2 and one wonders why one would need more than that from the accompanying control circuit.
Right off the top you could remove R12 and change R8 for a 470k - and probably get ok results. The open loop gain in the control circuit would be 47, which meets our minimum of 22. And taking out the very high gain from U7 might settle the circuit down enough to be stable right there.
If you had to put more DC gain in, you could put a resistor in parallel with C1 to limit the DC gain to something reasonable like 100, eg a 1000k in parallel with C1. But you may not need it if the 470k for R8 above got you acceptable results.
In terms of the accuracy you need: this circuit is driven by a micro+DAC. Ok, perhaps a calibration could be stored in the micro to correct a small %age error in the analog circuit. You might be able to live with more than 1% FS for the error in such case because the micro can correct for that.
In terms of the number of opamps, it is possible to provide the function needed with less micros. From the circuit above I would retain the unity buffer U4. A similar unity buffer is perhaps required on the DAC output. A 20k input impedance may be too much for the DAC output. A third opamp can produce Vgate from the 2 buffered signals. But unless you are tight for cost or board area then the circuit above is ok.
In terms of the simulation, you can put a AC frequency sweep voltage source IN SERIES with R9. Then look at the signal out U5-output that results from the series AC voltage source. Check the gain and phase margin through the process and control loop combined to ensure a robust, stable control.