Electrical – Opamp with multiple feedback loops

This was already mentioned by Russel, but I hope to present it in a different way.

The main problem here, it seems to me, is that your book (or whatever source of information you're using) missed one important point: The voltage between inverting and non-inverting inputs of an ideal operational amplifier should always be zero with this and similar setups. If we include that assumption and take a look at the circuit, we can get a logical answer.

The output of an op-amp is modelled as an ideal controlled voltage source. The input impedance is infinite and no current flows into the op-amp. So far so good. Next, we know that the voltage between the inputs is zero, so we know that the voltage with respect to ground and the inverting input is same as the one on the non-inverting input. That voltage comes from the ideal controlled voltage source at the output. Next, let's take a look at the current issue. Since we have infinite input impedance, no current flows into the operational amplifier, so from where does the output current come? Well from the ideal controlled voltage source at the output.

As I said, the voltage source is ideal, so it can source infinite current, it's controlled so you have your gain, the current is set by resistor and there's no contradiction there at all. In reality, the current will come from the power supply pins and be limited by construction of the operational amplifier, but this is a mathematical model. So let's take a look at a pretty pictures now:

The first image may seem a bit drastic:

I've crossed out the op-amp on purpose here. It seems to me that trees are obstructing your view of the forest here. If we remove the op-amp symbol and take a look at how we're supposed to model it instead (note the \$ 100 \mbox{ }G \Omega \$ resistor):

We can clearly see that the current is coming from the one terminal voltage source which is the output of the op-amp.

Next, I'll show a bit more complex version of the same circuit and explain how it degenerates into what you've shown:

Let's see what we can see here:

We've got the input voltage \$U_i\$, the output voltage \$U_o\$ and the resistors \$R_1\$ and \$R_2\$.

Now we know from our model that the voltage between the inputs is zero, so we can write following safely: \$U_i-R_1I=0\$, since the resistor \$R_1\$ has a short circuit to inverting input. From that we get the current: \$I=\frac{U_i}{R_1}\$. The current can only come from the op-amp output in this case, so we know that it is the current going through the resistor \$R_2\$ too. From that we get the equation for the output voltage of the op-amp: \$ U_o-R_2I-U_i=0\$ and after that: \$U_o=R_2 I + U_i= R_2 \frac{U_i}{R_1} + U_i=U_i(\frac{R_2}{R_1}+1)\$. From this, we have \$ \frac{U_o}{U_i}=1+ \frac{R_2}{R_1}\$. In the circuit you showed, equivalent elements would be \$R_2=0\$ and \$R_1=\infty\$. As you can see, the output current isn't a problem with this setup and again, there's no contradiction here.

With the few assumptions I've shown and few equations, you can do basic op-amp circuits without any problems. I recommend that you read from freely downloadable books Amplifiers and Bits: An Introduction to Selecting Amplifiers for Data Converters pages 6 and 7 and from Op Amps for Everyone Design Guide chapter 3 (or at least take a good look at the pictures there). Both books (well, a book and an application report) are by Texas Instruments (a major op-amp manufacturer) and should come up on most popular search engines as the first response.

I'm going to hand wave over a lot of detail here, but the short answer is that your "b" is correct. You effectively have a race condition and in order to answer exactly what happens you need to know about the propagation delay of your logic (and if we want to really dive into the nitty gritty wire delay etc). You would need to know how the 3 bit counter is implemented (e.g. with which gates and how those gates are implemented) and the propagation delays of the gates. You can think of the propagation delay of the gate as the "delay" of the gate. For example, if you take an inverter and toggle the input there's some delay till the output stabilizes. Take a look at this data sheet and search for "tphl" and "tplh". Notice that the two propagation times are not equal.

It is not necessarily true (in fact it is very probably necessarily not true) that all outputs of the counter toggle at the exact same time. Some outputs (depending on the implementation the more significant bit outputs) will require more logic and thus probably have a greater combinatatorial path to path to output (read more propagation delay). Furthermore there is no reason to assume that the inputs to the counter start at 3'b000. With these two facts the output of the counter will run around like crazy (the shortest combinatorial path way will gate the max output frequency e.g. the shortest combinatorial path will limit how fast the fastest output bit changes). Your display won't be able to keep up with the counter and will effectively display "random" numbers (obviously what the display actually shows depends a lot on its implementation).

For a simplistic, but similar example google "ring oscillator" (but don't build one unless it's for educational purposes only!) and "propagation delay of logic gates".