Electrical – Overlapping clock and data edges in multiple state machine designs

The easiest way to prove that two FSM's are equivalent is to minimize both and see if the results are the same.

To do this, you can use the partitioning minimization procedure as explained in section 8.6.1 of Fundamentals of Digital Logic.

Without going into too much detail, I will illustrate this procedure for your left state machine. The idea is to partition all states in such a way that states in the same partition are equivalent.

We start by assuming that all states may be equivalent by partitioning the states into one partition. Before doing this, note that states B and F are unreachable and can be deleted from the FSM. Therefore, the first partition is as follows:

$$P_1 = (ACDE)$$

The next step is to create groups of states with the same output value. This gives the following partition:

$$P_2 = (ACE)(D)$$

Next, we have to make sure that all the 0-successors of the states in a group are contained in one group (the same holds for the 1-successors). For example, the 0-successors of (ACE) are (DAA) which are not contained in a single group. Therefore, the group (ACE) needs to be split:

$$P_3 = (A)(CE)(D)$$

Since both the 0-successors (AA) and the 1-successors (EC) of (CE) are contained within one group, this partition does not need to be split anymore. This final partition learns us that states C and E are equivalent and we need three states in the minimal FSM.

Now we can introduce names for the new states: S1 = (A), S2 = (CE) and S3 = (D) and construct a new state table:

-------------------------
Current Next state Output
State     0    1
-------------------------
S1        S3   S2     0
S2        S1   S2     0
S3        S2   S1     1
-------------------------

Doing the same for your right state machine gives the following partition: $$P = (ACE)(D)(BF)$$

Using the state assignment S1 = (ACE), S2 = (D) and S3 = (BF) gives exactly the same state table as above. Hence, the two state machines are equivalent.

$$\blacksquare$$

So this code generates a 200 Hz clock based on a 100 Mhz clock.

We note that: 100 MHz / 500000 = 200 Hz

So, we need to take our 100 Mhz clock, and every 500000 cycles, we would have a full cycle of the 200 Hz clock that we would like to generate. Since we want the high time and low time to be the same, we know that we should oscillate the new clock every 500000 / 2 cycles.

From the perspective of the code, we will use hexadecimal, so it's worth noting that 500000 / 2 == 0x3D090.

architecture foo of blah is
    signal clk_200Hz : std_logic := '0';
    signal counter : unsigned(19 downto 0) := x"00000";
begin

    clkdiv : process (clk_100Mhz)
    begin
        if rising_edge(clk_100Mhz) then
            if counter = x"00000" then
                counter <= X"3D090"
                clk_200Hz <= not clk_200Hz;
            else
                counter <= counter - 1;
            end if;
        end if;
    end process clkdiv;

end architecture;