Looking at laying out a PCB that will utilize PCIE. I've read that you want to keep intra-pair trace length to 5mils max and that inter-pair trace length matching is not terribly important. The current plan was to keep all Tx pairs within 100mils and all Rx pairs within 100mils, but what I'm not sure about is how close to the same length the Tx pairs, Rx pairs, and Clock pair have to be. I read one site that said that up to a 3" difference is acceptable but that seems rather large to me.
Electrical – PCIE Trace Length Matching Between Tx, Rx, and Clock
pcbpcie
Best Answer
From Wikipedia
The allowed skew between the databytes in one direction is 6ns for 8 GT/s. Rx and Tx length matching is not critical as there is wide allowed duration. Assume it as a full duplex communication. How much exactly depends on the data link layer but definitely okay with 3 inch or so. Assuming 160ps per inch of propogation delay, the the 3 inch propogation delay will be about 0.5 ns. (Less than 2 ns)