First all below concerns only CMOS gates with switching point at 1/2 of Vcc. So, not HCT series. HC series are OK and 4xxx too.
At first, R1 does not affect the frequency at all. It is placed there in order to make the input current of the inverter (through the protection diodes) to not affect the work of the schematic. That is why it should be much bigger than R2.
The frequency of the schematic is \$F=\frac{1}{2.2.R_2.C_1}\$
How it is derived?
simulate this circuit – Schematic created using CircuitLab
At first notice that the voltage in points 2 and 3 can be only 0 or Vcc.
The schematic turns in the other stage when V1 is equal to the half of the power voltage.
When the second gate output flips from 1 to 0, the capacitor is charged to -0.5Vcc (the left plate is negative), so V1 becomes -0.5Vcc and starts to increase because R2 is connected to Vcc:
$$
\tau = R_2.C_1
$$
$$
V_1 = V_{cc}.(1-e^{-\frac{t}{\tau}})-\frac{V_{cc}}{2}.e^{-\frac{t}{\tau}} = V_{cc} - \frac{3.V_{cc}}{2}.e^{-\frac{t}{\tau}}
$$
The switching of the schematic will happen when V1 becomes equal to Vcc/2, so:
$$
\frac{V_{cc}}{2} = V_{cc} - \frac{3.V_{cc}}{2}.e^{-\frac{t}{\tau}}
$$
Or:
$$
\frac{V_{cc}}{2} = \frac{3.V_{cc}}{2}.e^{-\frac{t}{\tau}}
$$
$$
\frac{1}{3} = e^{-\frac{t}{\tau}} => 3 = e^{\frac{t}{\tau}}
$$
$$
ln 3 = \frac{t}{\tau}
$$
$$
t = \tau.ln 3 = R_2.C_1.ln 3 = 1.098612289.R_2.C_1
$$
This is the half of the period (because the schematic switches exactly on the half of the Vcc), so the period:
$$
T = 2.t = 2.197224577.R_2.C_1
$$
BTW: This oscillator has very high frequency stability, both, by the temperature and by the Vcc. This way its use have to be encouraged for all schematics where quartz stability is not needed.
The discrete transistorized astable and 555 astable circuit are about the same in complexity, so that's a wash. Here's the circuit for the 555 astable. Two resistors instead of four; both use two capacitors. But you've got the 555, and you'll need an inverter on the output as I'll explain later.
The trick is calculating the timing values. The easiest way is to use on-line calculators available on the web. There are a ton of these for the 555; I like this one best. But I only found one for the discrete circuit (scroll down to "2. Transistor Astable Oscillator (with unequal pulse width)". Try as I might, I couldn't find component values to come anywhere close to your timing requirements (1800 second period, 5 second on time) for the transistorized version of the astable.
However the gotcha with the 555 is the minimum duty cycle is 50%. To get a duty cycle lower than that, you need to use an inverter (such as an NPN transistor, or a 74LS04 gate if you need more drive) on the output.
Using the 555 astable calculator, and picking common values for electrolytic capacitors and 1% resistors that are available:
C = 220 µF
R1 = 11.8 MΩ
R2 = 33.2 KΩ
You will end up with the following nominal values:
period = 1804 seconds (30.1 minutes)
off time = 5.0 seconds
duty cycle = 99.72%
which is very close to what you are looking for. However as brhans alludes to, the big problem is going to be the timing capacitor which has a ±20% tolerance. This means the timing could vary like this:
220-44 = 176 µF period = 1447 sec (24.1 min), off time = 4.0 sec
220+64 = 264 µF period = 2170 sec (36.2 min), off time = 6.0 sec
And this doesn't take into account variations in the resistor values, however they will be much less at ±1%. So you are going to have to accept the possibility of the timing values being quite a bit off, or fine tune your components, for example by a combination of two capacitors in parallel to get the desired value.
Best Answer
This is how it works. (even though I disagree with this academic example) 2nd stage pumps max current into diode, while saturated and charges cap so input reaches Vdd+Vf, ( depending on diode and ESR of CMOS family) then diode turns off and decays by natural logarithm to threshold \$v_t\$ ( exponential decay) thus the half period becomes...
\$\frac{1}{2}* \frac{1}{f} =T\$ (=7.87us in my simulation)
\$T= RC*ln((V_{DD}+V_f) /v_t)\$
thus 100k*100e-12*ln((5+0.579V)/2.5V)= 8.03us with an discrepancy of 1.6%
Note the diodes I modeled here drop 580mV with 30mA spikes which can be a source of error as well as Vt and component tolerances.
Other details
The assumptions behind this model are flawed in so many ways, in reality with SCR Latchup effects if you exceed the absolute max input voltage. (Vss+0.5 and Vcc-0.5V) which is added for some ESD protection. I think they should ban this design for reasons of ESD diode stress, EMI egress, potential CMOS latchup and spurious oscillations on faster devices, , but don't sweat it
The actual CMOS devices come with Schottky diodes in two stages . They must be small to have react fast so they are all rated for 5mA max which is less than the drive current possible for some CMOS drivers. So this circuit is poor design to follow, but can be improved to protect ESD diodes or add much bigger Schottky diodes. But then this is not very efficient and causes large current spikes)
I had to add 50R output to simulate 74HC gate output impedance and add 50pF to prevent spurious oscillation just before toggle.
But to analyze the circuit , looks at the differentiate pulse which decays to Vcc/2 then toggles polarity. So the Peak Voltage at the input of 1st gate (in simple theory) is Vf+Vdd and thus this decays to Vdd/2 for the Time constant From my experience , I can ballpark estimate the ESR of any forward diode such that if it is rated for 5mA @0.5V ( the absolute max outside Vdd,Vss before latchup will occur) this is equivalent to an ESR of <=100 Ohms at rated current.
Thus in my simulation with 100pF cap and 50R ESR and 100R diode the Cap "dv/dt" charge time current spike is 15 ns wide with 2~3ns rise time. ( which spews spectrum from clock rate up to 1/15ns=66Mhz and then harmonics above that to 1/(2~3ns)= 333MHz to 500MHz.. Nasty crosstalk....
Some diodes in newer devices may be rated for 20mA steady absolute max.
A simpler circuit uses a Schmitt gate Inv or NAND with 1 gate and a feedback R and C input to gnd with a triangle wave on input from 1/3 to 2/3 Vdd instead of a differentiated diode clipped signal decaying across Vdd/2 +/- 30% over temp