High side switching is always tricky. There are no easy and simple ways, only various tradeoffs.
PMOS transistors are nice in that they can work within the existing voltage. The gate voltage needs to be pulled below the input voltage by 12-15 V to turn them fully on. The downside is that P channel MOSFETS usually have a little worse characteristics than the equivalent N channel.
N channel may have a better combination of Rdson, voltage tolerance, and cost, but require you to somehow make a voltage higher than the input to drive them. Some high side FET driver chips include a charge pump or other trick for this purpose. Another downside of a N channel high side switch is that the gate must swing a much larger amount, from zero to 12-15 volts above the input. This is because the gate voltage is relative to the source, which is now riding up and down with the voltage being switched. This requires high slew rates to stay out of the partially on region as much as possible, and provides more opportunity for noise pickup elsewhere.
There is no easy solution.
However in your particular case you may not need a high side switch at all. As W5VO mentioned in a comment, a flyback topology only requires a low side switch on the primary. The high side can stay connected to the input voltage.
A center tapped primary with the transformer run in forward mode is another possibility. The center tap goes to the input voltage with a low side switch pulling each end alternately to ground. Again there is no free lunch, which in this case is exhibited by the low side switches now having to withstand twice the input voltage. This is why the center tapped topology is more used for lower input voltages and usually not for worldwide "universal" power, which needs to handle up to 260 V AC or so. That would mean 368 V peaks, and 735 V stress on the low side switches. Transistors with that kind of voltage capability give up other parameters, like gain in bipolars and Rdson in FETs.
There is no free lunch.
Added:
I meant to say this earlier but somehow it slipped thru the cracks. You will most likely need a transformer anyway to get isolation. Unless you really really know what you're doing, you want the resulting supply to be isolated from the power line. The main exception is if the power stays completely inside a sealed box and there is not even a ground connection to the outside world. Otherwise, you run the risk of a user getting connected to the hot side of the AC line should even a few simple things go wrong. There is good reason commercial power supplies are mostly isolated.
Given that you probably want isolation, the problem becomes how to drive a transformer as apposed to how to make a buck switcher directly.
It depends on the crystalline structure of the epitaxial wafer and junction geometry and square of the current needed for bias in both conductor and dielectric. Flicker Noise is random pink noise usually measured <100Hz in \$A^2/Hz \$ as 1/f noise, but contributes to phase noise in RF.
- GaAs can be much better or worse than Si.
- carbon resistors are worse than metal film which are worse than copper resistors which are worse than "NP0" manganin conductors considered flicker noise-free.
The explanation is simple but hard to visualize.
Imagine a small low leakage cap on a unijunction gate or a DIAC with a small bias current and a breakdown voltage for the semiconductor shorting out the cap and then charging up again. This is a fixed f relaxation oscillator. Now imagine that certain semiconductor crystals have a higher leakage current (Early Effect) with greater BDV generating bigger partial discharges between charged molecules before they break down under the electric field (in a nano scale ) . Then imagine millions of relaxation oscillators of random pulse rate low pass filtered by the dielectric between the charged conductor atoms. So this RC time contant affects the relaxation rate while the high series leakage and shunt capacitance low pass filters these broadband pulses or "flickers".
So in my theory, it is the device with the highest RC leakage time constant and highest BDV where the product produces a corner frequency at some A^2/Hz with applied bias voltage. I call this flicker, random (PD) or partial (nano crystalline) discharge , for your understanding and consideration.
Which device?. depends on conduction power, leakage input bias current, dielectric doping levels, crystalline épiwafer nano-structure and meta structure such as FET, BJT or HJT.
But we know for sure how to rank conductors as I did above so we generally use MF for lower noise exclusively and carbon or WW where high current noise does not matter.
I don't know how to tell you which device has lowest random flicker noise for ANY random design.
... but you may look at GaAs FETs and compare.
Best Answer
The answer lies in the mean time between collisions and this is based on mobility. Whichever device has a higher mobility, \$\mu\$, will have higher collisions because you have a greater probability of have a collision. This generally means that nFETs have higher collisions and therefore higher flicker noise, but on undoped channels, you will see similar mobilities. I have 10nm fins on my bench that show higher \$\mu_p\$.
Due to Brownian motion, you have movement whenever you have heat, and skipping a bunch of physics, you end up with the average net velocity for drift to be \$v_{dn}= -\mu_nE\$ and \$v_{dp}= \mu_pE\$ respectively. The mobility \$\mu_x\$ has the "mean free time between collisions" term of \$\tau_c\$, as \$\mu_{n,p}=\frac{q\tau_c}{2m_{n,p}}\$.
Once you calculate \$\tau_c\$, what this tells you is that for a field, \$E\$, for similar devices you will have more collisions just due to higher mobility. To actually calculate \$\tau_c\$, you will need to pull out a device physics book and look at the density of states at a temperature under field conditions. This is one of those things that we just empirically measure. The math says it's proportional to \$T^{\frac{1}{2}}\$, but on the bench you see \$T^{\frac{3}{2}}\$ as your channel changes.