Electrical – protection of industrial analog input modules for high-voltage signals

circuit analysiscircuit-protection

I'm looking at ways to design a multi-functional analog input that can take both voltage and current inputs for industrial applications. The voltage signals are in the 0-40V range and the current signals are 4-20mA loops. I have found a few reference designs that seem to accomplish this (usually for 0-10V and 4-20mA signals) by switching on/off the current loop resistive load. Since I want to be able to take in up to 40V, I could add a voltage divider. I found the following schematic for a reference PLC module (enclosed in a rectangle is the part I'm interested in):

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Source: http://www.analog.com/media/en/technical-documentation/application-notes/an-1522.pdf

The above schematic is not rated for 40V input signals, but the approach used is similar to what I have in mind. My concern is on how to protect the circuit from user mistakes. I will use this schematic as a reference and forget about the 40V that I want for a second.

There are two basic scenarios that shouldn't happen, but can happen:

1) A voltage is fed when in current input mode (resistive load on): in this case, as long as R1 can handle the power it should be fine. For 10V that is 400mW, so no big deal. If the input signal can't source enough current the system will give a wrong reading, but as long as nothing gets burnt in my circuit I'm happy.

2) A current signal is fed when the circuit is voltage input mode: this case is the one I find more critical. Here is where I'm not sure what happens, and where my question comes. If R1 is not connected, and let's assume we have 20mA coming in, this will go through the voltage divider, and the resistors (assume 1 watt at best) won't be able to handle this power. Also, the output voltage of the voltage divider will be too high, and I'm not sure those clamping diodes will handle it? I'm not sure what happens in this scenario and whether the circuit is protected or if it will just explode. I would like somebody to help me understand exactly what would happen in this scenario, and see if I can extend this approach to work with my 40V signals requirement.

Best Answer


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Conceptual design for a balanced differential input of cascading clamps to reduce worst case power and provide best case overvoltage protection.

Most CMOS has the 2 stage diode clamp method inside for ESD protect of 3kV from 100pF or 5~10mA DC max.

To reduce Common Mode impulse noise or RF.


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