analogcircuit analysistransistors
I have this circuit:
can someone explain how this circuit works?
I did Ppsice simulation for the circuit and the results:
I don't understand how this circuit works, on the simulations its clear that it takes Sine wave and the output is amplified square wave with the same frequency, But how it does it?
does this circuit better than the circuit suggested on this topic: Sine wave to square wave – Schmitt trigger
??
What is the purpose of Q8 on the Scheme?
Any waveform other than a sine at 12.5 MHz will be composed of the fundamental frequency 12.5 MHz, plus harmonics above that. For ideal waveforms with sharp edges, the harmonics extend to infinity.
It sounds like you have added a filter with a cutoff frequency around 12.5 MHz, so this is why your non-sinusoidal outputs don't look like they should -- your filter is stripping off the harmonics which give those waves their non-sinusoidal identity.
To illustrate, here are a few animations from Wikipedia which show various non-sinusoidal waveforms as harmonics are added/removed:
What your filter should be doing is stripping off the harmonics generated by the impulses at each sample output by your DAC. This is called an anti-aliasing filter, and ideally it's a brick-wall low-pass filter with a cutoff equal to half your sampling frequency. Given that true brick-wall filters aren't realizable, the cutoff is usually a bit below half the sampling frequency, and the roll-off is made as steep as feasible. If you can sample significantly more than twice the highest frequency of interest, then the filter design isn't as critical.
It also follows that if you want to synthesize a 12.5 MHz square (or triangle, or sawtooth...) wave, you need a DAC sampling fast enough to also synthesize the higher harmonics in that wave. How much higher depends on how closely you want to approach an ideal square/triangle/sawtooth wave.
The reason for the sawtooth shape at the collectors of the transistors is caused by the B-E junction of the transistors and C1 / C2.
You can insert resistors in series with the base of each transistor - I'd start with 10k and see what happens. Be sure that the resistors are in series directly at the base of each transistor. That should give you a much more square-looking waveform at the transistor collectors.
The reason the sawtooth waveform happens is that the E-B junction of the transistors looks like a very-low impedance when the capacitors are charging via the 1k collector resistors. Think of it this way: the capacitors are almost in parallel with the collector E-C leads. There is a 0.6V region when the capacitor is beginning to charge that is high-impedance but as soon as the E-B voltage reaches 0.6V, the impedance drops to a very low value.
Best Answer
Using the simulation schematic:
Q1 and Q2 form a switchable constant current source.
As a result the output will switch from 0 mA to 70 mA maximum (if the load resistance is less than about 150 Ω).
The only bit remaining is understanding the operation of U1. From the Electrical Characteristics and Figure 1 of the 2N7002 datasheet we can see that the device will turn on with about 2.1 to 3 V applied to the gate. This will cause the drain-source resistance to drop to only a few ohms (see Figure 2). Thus U1 acts much like a relay would but controlled by the AC voltage applied.