Electrical – SPI internals _ missing MISO clock during read operation

spi

I am currently writing C++ code to utilize SPI protocol.
I am using popular library as a guide.
Run into few questionable areas and after some discussion on the library board forum I have been told "it is an internal problem " ( of the hardware ).
To be specific – using MOSI "port" I can "write" to hardware and monitor the outcome via software. Neither MOSI or CLK ports are connected to any SPI slave device. I have no issues there.
When I "read" MISO port,again not connected to slave device , I do expect no valid data – no actual MISO signal. That is fine.

However

The master DOES NOT send CLK at all!
The master / device empties buffer(s) which are filled DURING the "write" cycles DURING "read" from slave operation.

My actual general question I would like to get answered is

Does SPI master require physical connection to slave to send CLK to slave during slave read operations ?

Per SPI documentation – master sends CLK during "write" to slave and sends CLK during "read" from salve. Master SPI is the CLK source.
Only the SPI "write" part works as expected.

Best Answer

Your reference to SPI documentation already provides an answer. Yes, SCLK line is essential for communication, both to and from slave device.

I strongly advise to read that documentation again, it seems you did not understand how SPI works. To begin with, you cannot refer to individual MOSI/MISO/SCLK as "ports". They are communication lines that together form SPI bus, connected to SPI port. While in some cases MISO can be excluded, and SC can be permanently connected you do need at least MOSI and SCLK for sending commands to slave.