Electrical – Storing value of a conditional assignment in Verilog


Assume I have the follow assignment

wire COND;
assign COND = A & B;

The values of A and B are changing between true and false, however, once they both hit 1 at the same time and COND = 1; I wish to keep this COND as a true value (sort of like a trigger) instead of it reverting to 0 when A and B changes.

Does anyone know a neat way to accomplish this?
Thank you!

Best Answer

I've experienced simulators, synthesizers, linters, etc. that balk when they see an assign statement that directly assigns back to itself. They flag it because it is usually indicates an unintended latch.

Most design practices disarrange using (level sensitive) latches because prorogation delay could cause glitching leading to undesirable behavior. There are a few cases when a latch is necessary. In this situations the most common recommendations are:

  • use an always @* block (always_latch if SystemVerilog) separate from other combinational logic.
  • minimize the logic on the enable pin(s); complex logic have higher changes of causing glitches
  • Assign with non-blocking assignment (preferred)
  • Be aware the synthesizers may need directives to map to a specific latch type (eg SR-latch, D-latch, D-latch w/ async reset/preset, etc)

Your latch should look something like this:

reg COND;
always @* begin
  if(A && B) begin
    COND <= 1'b1;

You will probably want an additional condition to reset the latch and you will need to design if set or reset should have higher priority.

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