Electrical – transistor negative edge-triggered detector

The synchronization block is used to capture a signal that is not synchronous with the system clock (clkio in that example) -- it is required for any synchronous logic and as far as you're concerned it is transparent other than the fact that it delays the signal seen by the edge detector by 2 clock cycles. It prevents an "illegal" (not clearly 1 or 0) from entering the core where it can cause havoc. If you're really curious I can explain metastability and synchronizer chains but for this specific question I think that's overkill.

The edge detector block is simpler. The trapezoidal shape is a MUX, as Michael Karas mentioned. It allows the block to find either rising edges or falling edges. The flip flop is sampling the output of the MUX every clock cycle and essentially "remembering" the last value (1 or 0). The final AND gate is comparing the last value remembered by the flip flop and the inverted current value and will ONLY be high for 1 clock cycle if the signal changed state.

Look at how the output of the flip flop delays the input of the flip flop by 1 clock cycle:

 IN:  0000111100001111000011110000...
OUT:  0000011110000111100001111000...

Now take a look at signal that is the bottom input of the AND gate and the output of the FF above:

INV. FF INPUT:  1111000011110000111100001111...
    FF OUTPUT:  0000011110000111100001111000...

Take a look at the logic of an AND gate:

 A | B | Y
---+---+---
 0 | 0 | 0
 1 | 0 | 0
 0 | 1 | 0
 1 | 1 | 1

One of those inputs is the output of the FF, the other is the output of the inverter... What do you see:

INV. FF INPUT:  1111000011110000111100001111...
    FF OUTPUT:  0000011110000111100001111000...
--------------------------------------------------
 AND GATE OUT:  0000000010000000100000001000...

You get one short pulse every falling edge of the input to the edge detector block (assuming the MUX is routing the non-inverted signal to you). If the MUX selects the inverted signal, you will get a short pulse every rising edge of the input.

Quoting the MAX366 datasheet:-

"When signal voltages exceed or are within approximately 1.5V of either power-supply voltage (including when power is off), the two-terminal resistance increases dramatically, limiting fault current as well as output voltage to sensitive circuits"

The slow edge starts when you get within 1.5V of the negative rail, so the part is behaving as it should. Without more knowledge of what is on the other side it's hard to tell what would help.

If you want to use the MAX366 you could use a comparator with a 2.5V reference, then you wouldn't care about what happens below 1.5V or above 3.5V. You could even have some hysteresis so slow rise/fall would give a clean trigger pulse (a few comparators have hysteresis built in). Or just use a NC7WZ14P6X, which I think would give you enough margin (but check).