Electrical – Undefined std_logic_vector size parameter in procedure

fpgahdlsimulationvhdl

I have written into a procedure the behavior of a simple SPI transaction that I use in my testbenches to make things easier to write and read.
Is there a way to make this procedure as generic as possible by not mentioning the size of the vector data given as a parameter? Or maybe add a size parameter as an integer?

Here's the procedure I'm using so far. For now I have one procedure declaration for each vector size I want to transfer.

procedure spi_transfer_3B(data : std_logic_vector(23 downto 0)) is 
variable bitCnt : integer := data'length-1;
begin
    spi_clk <= '0';
    spi_mosi <= 'Z';
    spi_ss <= '0';
    wait until rising_edge(clk);

    for i in 2*data'length-1 downto 0 loop
        wait for SPI_CLK_PERIOD/2;
        spi_clk <= not spi_clk;
        if spi_clk = '0' then
            spi_mosi <= data(bitCnt);
            bitCnt := bitCnt -1;
        end if;
    end loop;

    spi_clk <= '0';
    wait until rising_edge(clk);
    spi_ss <= '1';
    spi_mosi <= 'Z';
end spi_transfer_3B;

What do you think?

Best Answer

This seems to work. I was confused because not mentioning x downto x coded the vector LSB first instead of MSB first as intended in my first snippet of code. It is that easy. 

procedure spi_transfer(data : std_logic_vector) is 
variable bitCnt : integer := 0;
begin
    spi_clk <= '0';
    spi_mosi <= 'Z';
    spi_ss <= '0';
    wait until rising_edge(clk);

    for i in data'range loop
       wait for SPI_CLK_PERIOD/2;
       spi_clk <= '1';
       spi_mosi <= data(i);
       wait for SPI_CLK_PERIOD/2;
       spi_clk <= '0';
    end loop;

    spi_clk <= '0';
    wait until rising_edge(clk);
    spi_ss <= '1';
    spi_mosi <= 'Z';
end spi_transfer;
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