Electrical – Use floating values in VHDL code

fixed-pointfpgavhdl

Assume I want to have a continous sine signal as input to my VHDL code. The values will be of type float since it will take on non-integer values for example: 10.5 mA.

How do I manage these numbers in my VHDL code?

I have tried to use: type Voltage_Level is range -5.5 to +5.5; as an example but it did not work since i couldn't import signed vector into Voltage_level since Voltage_level must be represented as a signal.

I would appreciate if someone could help with these kind of issues? What is the most easiest way to deal with this?

The basic problem is when I input non-integer values, say 10.5 and try to use the same value as input the FPGA outputs a rounded integer, in this case 10. So it seems that I can use VHDL only when i deal with integers and bit vectors, which is very limiting use scenario. Especially for people like me that work a lot with various kinds of signals.

Best Answer

Try using fixed point notation instead. Float point is bit tedious in VHDL. Since your range is not wide, you can use Fixed point representation. To see more about the fixed point visit : http://vhdlguru.blogspot.in/2010/03/fixed-point-operations-in-vhdl-tutorial.html

Related Solutions

Constraining unconstrained integer in record on use

I'm not aware of any way to "post-constrain" an integer like that.

However, in my experience, the synthesis tools will take note of the source of the data that you write to any integer down the line (presumably irrespective of whether the integer is in a record or not, but I haven't tried it) and propagate any constraints from that source onto the destination.

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Best Answer

Related Solutions

Constraining unconstrained integer in record on use

Electronic – VHDL logical operation on integer

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