Electrical – Using both Synchronous and Asynchronous resets in a design


I am working on an FPGA design in which I also have to integrate several legacy IP cores. I use asynchronous assertion and synchronous de-assertion for the master reset signal in my design.
I observed that some of the IPs I got use synchronous resets while the others use asynchronous resets.

Will this create any issues during design implementation?
Do I have to modify the IPs to use a common reset method or can I just ignore this? (I have some restrictions in modifying some of the IPs)

Best Answer

If I have a design with synchronous reset, and you feed it with an async reset signal which may be asserted at any time, it internally goes via a clocked flip-flop. So for the design, it will be just like a synchronous reset. So it has to work.

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