Electrical – Using negative clock edge in phsical design

clockdigital-logicnegativeverilog

In Verilog, is it ok to use negedge of clock. Can a memory element be triggered at the negedge of clock? How robust will be the design practically in the chip?

Best Answer

Internal memory blocks (e.g. M9K) are clocked at positive edge of the clock, thus they will do nothing on negative edge of the clock.

But you can feed inverted clock to the M9K block's clock input. For example, you have circuit built using always block which uses posedge of the clock to set memory address, data to write and control signals, and then, on following negedge, if you feed the same clock inverted into RAM block, RAM block will sample its input wires (address, data, control) and perform requested operation. I would view this type of operation as "waterfall" (not sure if there's any special term for it).

But there're downsides of it:

half period of clock must be long enough to have RAM input lines stable; e.g. in my experience for M9K single 1024x9 block I had configuration working properly at 8.8 ns clock, but two blocks combined did not work properly, thus I had to extend clock cycle twice;
data read from the RAM may appear not on the next rising edge of master clock, but in the second rising edge (because RAM operation is delayed half-clock). Again, if half-cycle of clock is long enough for RAM to retrieve its contents within time of half of the clock, you can sample data on next master clock rising edge, if not, you must have one spare cycle;
inverting clock at the input to RAM block will introduce very small delay, you should also take it into account.

If you have other devices rather than M9K blocks in mind, then you should refer to their datasheets and timing.

Related Solutions

Electronic – Using both edges of a clock

When you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock.

In order to do what you want, you are going to need to have two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

For example, one always block could contain your programmable divider. Design it so that the output duty cycle is less than 50% when given an odd number. Use the second always block (on the other clock edge) to delay the output of the first block by 1/2 clock, then OR the two outputs together. Disable the output of the second block for even divider values.

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

The Instanitation template gives you an example of how to use the core in your project. All you need to do is paste it into your verilog file.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
                         ^ Change the signals in brackets to your signals
     ^ You don't need to change the port names
    .CLK0_OUT(CLK0_OUT)
);

To help you match it up with the tutorial, in VHDL, it looks like this:

DCM32to50_i : DCM32to50 
port map (
CLKIN_IN        => CLKIN_IN,
CLKFX_OUT       => CLKFX_OUT,
CLKIN_IBUFG_OUT => CLKIN_IBUFG_OUT,
CLK0_OUT        => CLK0_OUT);
                         ^ Signal name you can make what you want.
  ^ Port name doesn't change

CLKIN_IN is your input 32 Mhz clock
CLKFX_OUT is the new 25 Mhz clock
CLKIN_IBUFG_OUT is a buffered version of your 32 Mhz clock
CLK0_OUT is your input clock at 0 phase (basically your input clock again).

Best Answer

Related Solutions

Electronic – Using both edges of a clock

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

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