Electrical – verilog code with two falling edges

modulesynthesissystem-verilogverilogxilinx

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I have a problem with writing verilog for the following logic:
Consider clk and R3 are input signals & out is the output signal. At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1.
How can I implement this logic in verilog? I am stuck because it seems to me that there is no way to distinguish between falling edge of R3 and falling edge of clk.

At the falling edge of both clk and R3, both clk and R3 are equal to 0 so I can't distinguish them.

    module startup(clk, R3, out); 
   input clk, R3; 
   output reg out; 
   always@(negedge clk, negedge R3) begin 


   end 
   endmodule

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Best Answer

Each input requires its own process. Create two "toggle" FFs, and then XOR their outputs together. Toggle the "set" FF when the output is zero, and toggle the "reset" FF when the output is one.

module dual_edge_ff (
  input set,
  input reset,
  output q
);
  reg set_ff;
  reg reset_ff;
  assign q = set_ff ^ reset_ff;

  always @(negedge set) if (!q) set_ff <= !set_ff;
  always @(negedge reset) if (q) reset_ff <= !reset_ff;
endmodule

If you're building this with discrete logic, you just need a 74xx73 (dual negative edge triggered JK FF) and a 74xx86 (quad XOR gate, use one section as an inverter).

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