Let's say that we want to do a good job of testing this, but without going through the entire 2^32 space of possible operands. (It is not possible for such adder to have such a bug that it only affects a single combination of operands, requiring an exhaustive search of the 2^32 space, so it is inefficient to test it that way.)
If the individual adders are working correctly, and the ripple propagation between them works correctly, then it is correct.
I would giver priority to some test cases which focus on stressing the carry rippling, since the adders have been individually tested.
My first test case would be adding 1 to 1111..1111 which causes a carry out of every bit. The result should be zero, with a carry out of the highest bit.
(Every test case should be tried over both commutations: A + B and B + A, by the way.)
The next set set of test cases would be adding 1 to various "lone zero" patterns like 011...111, 1011...11, 110111..111, ..., 1111110. The presence of a zero should "eat" the carry propagation correctly at that bit position, so that all bits in the result which are lower than that position are zero, and all higher bits are 1 (and, of course, there is no final carry out of the register).
Another set of test cases would add these "lone 1" power-of-two bit patterns to various other patterns: 000...1, 0000...10, 0000...100, ..., 1000..000. For instance, if this is added to the operand 1111.1111, then all bits from that bit position to the left should clear, and all the bits below that should be unaffected.
Next, a useful test case might be to add all of the 16 powers of two (the "lone 1" vectors), as well as zero, to each of the 65536 possible values of the opposite operand (and of course, commute and repeat).
Finally, I would repeat the above two "lone 1" tests with "lone 11": all bit patterns which have 11 embedded in 0's, in all possible positions. This way we are hitting the situations that each adder is combining two 1 bits and a carry, requiring it to produce 1 and carry out 1.
VHDL accepts the ISO 8859-1 character set, this is UTF-8.
Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.
Your comments aren't delineated by two dashes (e.g. --
), your double quotation marks all need to be replaced with "
.
After which the VHDL code analyzes.
There's no discernible reason why d3
, d2
, d1
, and d0
can't be replaced with a bit_vector. There may uses with the present port interface in the book.
Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.
Converting between non-closely related types can be done with conversion routines:
-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
port(
d3, d2, d1, d0: in bit;
a, b, c, d, e, f, g: out bit
);
end entity;
architecture seven_segment of bcd_7seg is
signal input : bit_vector (3 downto 0);
signal output: bit_vector (6 downto 0);
begin
input <= d3 & d2 & d1 & d0;
with input select
output <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"1100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0001100" when "1001",
"1111111" when others;
-- separate the output vector to make individual pin outputs.
a <= output(6);
b <= output(5);
c <= output(4);
d <= output(3);
e <= output(2);
f <= output(1);
g <= output(0);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity bcd_tb is
end entity;
architecture foo of bcd_tb is
signal d: std_logic_vector (3 downto 0) := "0100";
signal output: std_logic_vector (6 downto 0);
begin
DUT:
entity work.bcd_7seg
port map (
d3 => to_bit(d(3)),
d2 => to_bit(d(2)),
d1 => to_bit(d(1)),
d0 => to_bit(d(0)),
to_stdulogic(a) => output(6),
to_stdulogic(b) => output(5),
to_stdulogic(c) => output(4),
to_stdulogic(d) => output(3),
to_stdulogic(e) => output(2),
to_stdulogic(f) => output(1),
to_stdulogic(g) => output(0)
);
end architecture;
You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.
Best Answer
You need to cast
cin
to an unsigned, then add it in.You'll end up with this:
Note that
resize
returns an unsigned here.